HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 476

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

13. Bus State Controller (BSC)
13.2.8
The memory control register (MCR) is a 32-bit readable/writable register that specifies RAS and
CAS timing and burst control for DRAM and synchronous DRAM (areas 2 and 3), address
multiplexing, and refresh control. This enables DRAM and synchronous DRAM to be connected
without using external circuitry.
MCR is initialized to H'00000000 by a power-on reset, but is not initialized by a manual reset or in
standby mode. Bits RASD, MRSET, TRC2–0, TPC2–0, RCD1–0, TRWL2–0, TRAS2–0, BE,
SZ1–0, AMXEXT, AMX2–0, and EDOMODE are written in the initialization following a power-
on reset, and should not be modified subsequently. When writing to bits RFSH and RMODE, the
same values should be written to the other bits so that they remain unchanged. When using DRAM
or synchronous DRAM, areas 2 and 3 should not be accessed until register initialization is
completed.
Rev.4.00 Oct. 10, 2008 Page 376 of 1122
REJ09B0370-0400
Initial value:
Initial value:
Initial value:
Initial value:
R/W:
R/W:
R/W:
R/W:
Memory Control Register (MCR)
Bit:
Bit:
Bit:
Bit:
TRWL2
RASD
TCAS
R/W
R/W
R/W
R/W
SZ0
31
23
15
0
0
0
7
0
AMXEXT
MRSET
TRWL1
R/W
R/W
R/W
30
22
14
—
R
0
0
0
6
0
TRWL0
AMX2
TRC2
TPC2
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
TRAS2
AMX1
TRC1
TPC1
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
TRAS1
AMX0
TRC0
TPC0
R/W
R/W
R/W
R/W
27
19
11
0
0
0
3
0
TRAS0
RFSH
R/W
R/W
26
18
10
—
—
R
R
0
0
0
2
0
RMODE
RCD1
R/W
R/W
R/W
BE
25
17
—
R
0
0
9
0
1
0
MODE
RCD0
EDO
R/W
R/W
R/W
SZ1
24
16
—
R
0
0
8
0
0
0