HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 656

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

14. Direct Memory Access Controller (DMAC)
• TDACK: Reply strobe signal for external device from DMAC
• ID1, ID0: Channel number notification signals
Data Transfer Request Format (DTR)
The data transfer request format (DTR format) consists of 32 bits. In the case of normal data
transfer mode (channel 0, except channel 0) and the handshake protocol using the data bus,
channel number and transfer request mode are specified. Connection is made to D31 through D0.
Bits 31 to 29: Transmit Size (SZ2–SZ0)
• 000: DTR format selected
• 001: Setting prohibited
• 010: Setting prohibited
• 011: Setting prohibited
• 100: Setting prohibited
• 101: Setting prohibited
• 110: Request queue clear specification
• 111: Transfer end specification
Bit 28: Reserved
Bits 27 and 26: Channel Number (ID1, ID0)
• 00: Channel 0
• 01: Channel 1
• 10: Channel 2
Rev.4.00 Oct. 10, 2008 Page 556 of 1122
REJ09B0370-0400
31
SZ
The assertion timing is the same as the DACKn assertion timing for each memory interface.
However, note that TDACK is an active-low signal.
⎯ 00: Channel 0
⎯ 01: Channel 1
⎯ 10: Channel 2
⎯ 11: Channel 3
(Reserved)
29
28
27
ID
26
25
MD
24
Figure 14.25 Data Transfer Request Format
23
(Reserved)
0