HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 744

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

15. Serial Communication Interface (SCI)
15.3.3
The multiprocessor communication function performs serial communication using a
multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous
mode. Use of this function enables data transfer to be performed among a number of processors
sharing a serial transmission line.
When multiprocessor communication is carried out, each receiving station is addressed by a
unique ID code.
The serial communication cycle consists of two cycles: an ID transmission cycle which specifies
the receiving station, and a data transmission cycle. The multiprocessor bit is used to differentiate
between the ID transmission cycle and the data transmission cycle.
The transmitting station first sends the ID of the receiving station with which it wants to perform
serial communication as data with the multiprocessor bit set to 1. It then sends transmit data as
data with the multiprocessor bit cleared to 0.
The receiving station skips the data until data with the multiprocessor bit set to 1 is sent.
When data with a 1 multiprocessor bit is received, the receiving station compares that data with its
own ID. The station whose ID matches then receives the data sent next. Stations whose ID does
not match continue to skip the data until data with a 1 multiprocessor bit is again received. In this
way, data communication is carried out among a number of processors.
Rev.4.00 Oct. 10, 2008 Page 644 of 1122
REJ09B0370-0400
RDRF
FER
Serial
data
1
Multiprocessor Communication Function
Start
bit
0
D0
Figure 15.11 Example of SCI Receive Operation
D1
(Example with 8-Bit Data, Parity, One Stop Bit)
One frame
Data
D7
RXI interrupt
request
Parity
bit
0/1
Stop
bit
1
Start
bit
0
SCRDR1 data read and
RDRF flag cleared to 0
by RXI interrupt handler
D0
D1
Data
D7
Parity
bit
0/1
ERI interrupt request
generated by framing
error
Stop
bit
0
0/1