HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 691
HD6417751RF240V
Manufacturer Part Number
HD6417751RF240V
Description
MPU 1.5/3.3V 0K PB-FREE 256-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417751RBP200DV.pdf
(1226 pages)
Specifications of HD6417751RF240V
Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-QFP Exposed Pad, 256-eQFP, 256-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417751RF240V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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14. Direct Memory Access Controller (DMAC)
Bit 17—Acknowledge Mode (AM): In dual address mode, selects whether DACK is output in the
data read cycle or write cycle. In single address mode, DACK is always output regardless of the
setting of this bit.
In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, it is valid in
CHCR0–CHCR7. (DDT mode: TDACK) For details of the settings, see the description of the AM
bit in section 14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3).
Bit 16—Acknowledge Level (AL): Specifies the DACK (acknowledge) signal as active-high or
active-low.
This bit is valid only in CHCR0 and CHCR1 in normal mode, and is invalid in DDT mode. For
details of the settings, see the description of the AL bit in section 14.2.4, DMA Channel Control
Registers 0−3 (CHCR0−CHCR3).
Bits 15 and 14—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify
incrementing/decrementing of the DMA transfer destination address. The specification of these
bits is ignored when data is transferred from external memory to an external device in single
address mode. For details of the settings, see the description of the DM1 and DM0 bits in section
14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3).
Bits 13 and 12—Source Address Mode 1 and 0 (SM1, SM0): These bits specify
incrementing/decrementing of the DMA transfer source address. The specification of these bits is
ignored when data is transferred from an external device to external memory in single address
mode. For details of the settings, see the description of the SM1 and SM0 bits in section 14.2.4,
DMA Channel Control Registers 0−3 (CHCR0−CHCR3).
Bits 11 to 8—Resource Select 3 to 0 (RS3–RS0): These bits specify the transfer request source.
For details of the settings, see the description of the RS3−RS0 bits in section 14.2.4, DMA
Channel Control Registers 0−3 (CHCR0−CHCR3).
Bit 7—Transmit Mode (TM): Specifies the bus mode for transfer. For details of the settings, see
the description of the TM bit in section 14.2.4, DMA Channel Control Registers 0−3
(CHCR0−CHCR3).
Bits 6 to 4—Transmit Size 2 to 0 (TS2–TS0): These bits specify the transfer data size. For
details of the settings, see the description of the TS2−TS0 bits in section 14.2.4, DMA Channel
Control Registers 0−3 (CHCR0−CHCR3).
Rev.4.00 Oct. 10, 2008 Page 591 of 1122
REJ09B0370-0400
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