HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 918

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

20. User Break Controller (UBC)
20.5
Instruction Access Cycle Break Condition Settings
• Register settings: BASRA = H'80 / BARA = H'00000404 / BAMRA = H'00 /
• Register settings: BASRA = H'80 / BARA = H'00037226 / BAMRA = H'00 /
• Register settings: BASRA = H'80 / BARA = H'00027128 / BAMRA = H'00 /
Rev.4.00 Oct. 10, 2008 Page 818 of 1122
REJ09B0370-0400
BBRA = H'0014 / BASRB = H'70 / BARB = H'00008010 / BAMRB = H'01 /
BBRB = H'0014 / BDRB = H'00000000 / BDMRB = H'00000000 / BRCR = H'0400
Conditions set: Independent channel A/channel B mode
⎯ Channel A: ASID: H'80 / address: H'00000404 / address mask: H'00
⎯ Channel B: ASID: H'70 / address: H'00008010 / address mask: H'01
A user break is generated after execution of the instruction at address H'00000404 with
ASID = H'80, or before execution of an instruction at addresses H'00008000–H'000083FE
with ASID = H'70.
BBRA = H'0016 / BASRB = H'70 / BARB = H'0003722E / BAMRB = H'00 /
BBRB = H'0016 / BDRB = H'00000000 / BDMRB = H'00000000 / BRCR = H'0008
Conditions set: Channel A → channel B sequential mode
⎯ Channel A: ASID: H'80 / address: H'00037226 / address mask: H'00
⎯ Channel B: ASID: H'70 / address: H'0003722E / address mask: H'00
The instruction at address H'00037266 with ASID = H'80 is executed, then a user break is
generated before execution of the instruction at address H'0003722E with ASID = H'70.
BBRA = H'001A / BASRB = H'70 / BARB = H'00031415 / BAMRB = H'00 /
BBRB = H'0014 / BDRB = H'00000000 / BDMRB = H'00000000 / BRCR = H'0000
Bus cycle: instruction access (post-instruction-execution), read (operand size not included
in conditions)
Data: H'00000000 / data mask: H'00000000
Bus cycle: instruction access (pre-instruction-execution), read (operand size not included in
conditions)
Bus cycle: instruction access (pre-instruction-execution), read, word
Data: H'00000000 / data mask: H'00000000
Bus cycle: instruction access (pre-instruction-execution), read, word
Examples of Use