HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 992

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

22. PCI Controller (PCIC)
22.2.20 PCI Interrupt Register (PCIINT)
Note: WC: Cleared by writing “1”. (Writing of 0 is ignored.)
The PCI interrupt register (PCIINT) is a 32-bit register that saves the error source when an error
occurs on the PCI bus as a result of the PCIC attempting to invoke a transfer on the PCI bus, or
when the PCIC is the PCI master or PCI target. This register can be read from both the PP bus and
PCI bus. Also, 1 can be written from either the PP bus or PCI bus to perform a write-clear in
which the detection bit is cleared to its initial value (0).
The PCIINT register is initialized to H'00000000 at a power-on reset or software reset.
Rev.4.00 Oct. 10, 2008 Page 892 of 1122
REJ09B0370-0400
PP Bus-R/W:
PP Bus-R/W:
PP Bus-R/W:
PP Bus-R/W:
Initial value:
Initial value:
Initial value:
Initial value:
PCI-R/W:
PCI-R/W:
PCI-R/W:
PCI-R/W:
Bit:
Bit:
Bit:
Bit:
ADRPER
M_LOCK
R/WC
R/WC
R/WC
R/WC
ON
31
23
15
—
—
R
R
R
R
R
0
0
0
7
0
T_TGT_A
SERR_D
BORT
R/WC
R/WC
R/WC
R/WC
ET
30
22
14
—
—
R
R
R
R
0
0
0
6
0
T_DPER
R_WT
R/WC
R/WC
29
21
13
—
—
—
R
R
R
R
R
R
0
0
0
5
0
T_PERR_
R/WC
R/WC
DET
28
20
12
—
—
—
R
R
R
R
R
R
0
0
0
4
0
M_TGT_A
BORT
R/WC
R/WC
27
19
11
—
—
—
R
R
R
R
R
R
0
0
0
3
0
M_MST_
ABORT
R/WC
R/WC
26
18
10
—
—
—
R
R
R
R
R
R
0
0
0
2
0
TGT_RET
M_DPER
R_WT
R/WC
R/WC
R/WC
R/WC
RY
25
17
—
—
R
R
R
R
0
0
9
0
1
0
MST_DIS
M_DPER
R_RD
R/WC
R/WC
R/WC
R/WC
24
16
—
—
R
R
R
R
0
0
8
0
0
0