HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 71

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

19.3 Register Descriptions ........................................................................................................ 780
19.4 INTC Operation ................................................................................................................ 787
19.5 Interrupt Response Time ................................................................................................... 790
19.6 Usage Notes ...................................................................................................................... 791
Section 20 User Break Controller (UBC)
20.1 Overview........................................................................................................................... 795
20.2 Register Descriptions ........................................................................................................ 798
20.3 Operation........................................................................................................................... 808
19.3.1 Interrupt Priority Registers A to D (IPRA–IPRD) ............................................... 780
19.3.2 Interrupt Control Register (ICR).......................................................................... 781
19.3.3 Interrupt Priority Level Settting Register 00 (INTPRI00) ................................... 783
19.3.4 Interrupt Factor Register 00 (INTREQ00) ........................................................... 784
19.3.5 Interrupt Mask Register 00 (INTMSK00)............................................................ 784
19.3.6 Interrupt Mask Clear Register 00 (INTMSKCLR00) .......................................... 785
19.3.7 INTREQ00, INTMSK00, and INTMSKCLR00 Bit Allocation .......................... 786
19.4.1 Interrupt Operation Sequence .............................................................................. 787
19.4.2 Multiple Interrupts ............................................................................................... 789
19.4.3 Interrupt Masking with MAI Bit .......................................................................... 789
19.6.1 NMI Interrupts (SH7751 Only)............................................................................ 791
20.1.1 Features................................................................................................................ 795
20.1.2 Block Diagram ..................................................................................................... 796
20.2.1 Access to UBC Registers ..................................................................................... 798
20.2.2 Break Address Register A (BARA) ..................................................................... 799
20.2.3 Break ASID Register A (BASRA)....................................................................... 800
20.2.4 Break Address Mask Register A (BAMRA)........................................................ 800
20.2.5 Break Bus Cycle Register A (BBRA).................................................................. 801
20.2.6 Break Address Register B (BARB)...................................................................... 803
20.2.7 Break ASID Register B (BASRB) ....................................................................... 803
20.2.8 Break Address Mask Register B (BAMRB) ........................................................ 803
20.2.9 Break Data Register B (BDRB) ........................................................................... 803
20.2.10 Break Data Mask Register B (BDMRB).............................................................. 804
20.2.11 Break Bus Cycle Register B (BBRB) .................................................................. 805
20.2.12 Break Control Register (BRCR) .......................................................................... 805
20.3.1 Explanation of Terms Relating to Accesses......................................................... 808
20.3.2 Explanation of Terms Relating to Instruction Intervals ....................................... 808
20.3.3 User Break Operation Sequence .......................................................................... 809
20.3.4 Instruction Access Cycle Break ........................................................................... 810
20.3.5 Operand Access Cycle Break............................................................................... 811
20.3.6 Condition Match Flag Setting .............................................................................. 812
..................................................................... 795
Rev.4.00 Oct. 10, 2008 Page lxix of xcviii
REJ09B0370-0400