HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 470

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

13. Bus State Controller (BSC)
• When DRAM or Synchronous DRAM Interface is Set*
Note: * External wait input is always ignored
Bit 15: A3W2
0
1
Note:
Bits 11 to 9—Area 2 Wait Control (A2W2–A2W0): These bits specify the number of wait states
to be inserted for area 2. External wait input is only enabled when the SRAM interface or MPX
interface is used, and is ignored when synchronous DRAM is used. For the case where an MPX
interface setting is made, see table 13.7.
• When SRAM Interface is Set
Bit 11: A2W2
0
1
Rev.4.00 Oct. 10, 2008 Page 370 of 1122
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*
Inhibited in RAS down mode
Bit 14: A3W1
0
1
0
1
Bit 10: A2W1
0
1
0
1
Bit 13: A3W0
0
1
0
1
0
1
0
1
Bit 9: A2W0
0
1
0
1
0
1
0
1
DRAM CAS
Assertion Width
1
2
3
4
7
10
13
16
0
1
2
3
6
9
12
15 (Initial value)
Inserted Wait States
Description
Description
Synchronous DRAM
CAS Latency Cycles
Inhibited
1*
2
3
4*
5*
Inhibited
Inhibited
RDY Pin
Ignored
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled