HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 150

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

2. Programming Model
Rev.4.00 Oct. 10, 2008 Page 50 of 1122
REJ09B0370-0400
Notes: 1. The R0 register is used as the index register in indexed register-indirect addressing mode and
31
(a) Register configuration
2. Banked registers
3. Banked registers
4. Banked registers
in user mode
indexed GBR indirect addressing mode.
Accessed as general registers when the RB bit is set to 1 in the SR register. Accessed only by
LDC/STC instructions when the RB bit is cleared to 0.
Accessed as general registers when the RB bit is cleared to 0 in the SR register. Accessed only by
LDC/STC instructions when the RB bit is set to 1.
R0 _ BANK0*
R1 _ BANK0*
R2 _ BANK0*
R3 _ BANK0*
R4 _ BANK0*
R5 _ BANK0*
R6 _ BANK0*
R7 _ BANK0*
MACH
Figure 2.2 CPU Register Configuration in Each Processor Mode
MACL
GBR
R10
R11
R12
R13
R14
R15
SR
PR
PC
R8
R9
1
*
2
2
2
2
2
2
2
2
0
31
(b) Register configuration in
privileged mode (RB = 1)
R0 _ BANK1*
R0 _ BANK0*
R1 _ BANK1*
R2 _ BANK1*
R3 _ BANK1*
R4 _ BANK1*
R5 _ BANK1*
R6 _ BANK1*
R7 _ BANK1*
R1 _ BANK0*
R2 _ BANK0*
R3 _ BANK0*
R4 _ BANK0*
R5 _ BANK0*
R6 _ BANK0*
R7 _ BANK0*
MACH
MACL
GBR
SGR
SSR
VBR
SPC
DBR
R10
R11
R12
R13
R14
R15
PR
SR
PC
R8
R9
1
1
*
*
3
3
3
3
3
3
3
4
4
4
4
4
4
4
3
4
0
31
(c) Register configuration in
privileged mode (RB = 0)
R0 _ BANK0*
R0 _ BANK1*
R1 _ BANK0*
R2 _ BANK0*
R3 _ BANK0*
R4 _ BANK0*
R5 _ BANK0*
R6 _ BANK0*
R7 _ BANK0*
R1 _ BANK1*
R2 _ BANK1*
R3 _ BANK1*
R4 _ BANK1*
R5 _ BANK1*
R6 _ BANK1*
R7 _ BANK1*
MACH
MACL
GBR
SGR
SSR
VBR
SPC
DBR
R10
R11
R12
R13
R14
R15
PR
R8
R9
SR
PC
1
1
*
*
4
4
4
4
4
4
4
3
3
3
3
3
3
3
4
3
0