HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 738

MPU 1.5/3.3V 0K PB-FREE 256-QFP

HD6417751RF240V

Manufacturer Part Number
HD6417751RF240V
Description
MPU 1.5/3.3V 0K PB-FREE 256-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417751RF240V

Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-QFP Exposed Pad, 256-eQFP, 256-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417751RF240V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
15. Serial Communication Interface (SCI)
Rev.4.00 Oct. 10, 2008 Page 638 of 1122
REJ09B0370-0400
Write transmit data to SCTDR1
Read TDRE flag in SCSSR1
Read TEND flag in SCSSR1
Clear TE bit in SCSCR1 to 0
Clear SPB0DT to 0 and
All data transmitted?
Start of transmission
and clear TDRE flag
End of transmission
set SPB0IO to 1
in SCSSR1 to 0
Break output?
TDRE = 1?
TEND = 1?
Yes
Yes
Yes
Yes
Figure 15.8 Sample Serial Transmission Flowchart
No
No
No
No
1. SCI status check and transmit data
2. Serial transmission continuation
3. Break output at the end of serial
write: Read SCSSR1 and check that
the TDRE flag is set to 1, then write
transmit data to SCTDR1 and clear
the TDRE flag to 0.
procedure: To continue serial
transmission, read 1 from the TDRE
flag to confirm that writing is possible,
then write data to SCTDR1, and then
clear the TDRE flag to 0. (Checking
and clearing of the TDRE flag is
automatic when the direct memory
access controller (DMAC) is activated
by a transmit-data-empty interrupt
(TXI) request, and data is written to
SCTDR1.)
transmission: To output a break in
serial transmission, clear the SPB0DT
bit to 0 and set the SPB0IO bit to 1 in
SCSPTR, then clear the TE bit in
SCSCR1 to 0.

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