HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 330

MPU 1.5/3.3V 0K PB-FREE 256-QFP

HD6417751RF240V

Manufacturer Part Number

HD6417751RF240V

Description

MPU 1.5/3.3V 0K PB-FREE 256-QFP

Manufacturer

Renesas Electronics America

Series

SuperH® SH7750r

Datasheet

1.D6417751RBP200DV.pdf (1226 pages)

Specifications of HD6417751RF240V

Core Processor

SH-4

Core Size

32-Bit

Speed

240MHz

Connectivity

EBI/EMI, FIFO, SCI, SmartCard

Peripherals

DMA, POR, WDT

Number Of I /o

39

Program Memory Type

ROMless

Ram Size

48K x 8

Voltage - Supply (vcc/vdd)

1.4 V ~ 1.6 V

Oscillator Type

External

Operating Temperature

-20°C ~ 75°C

Package / Case

256-QFP Exposed Pad, 256-eQFP, 256-HQFP

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Eeprom Size

-

Program Memory Size

-

Data Converters

-

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

BOSTOCK HK LIMITED

Part Number:

HD6417751RF240V

Manufacturer:

Renesas Electronics America

Quantity:

10 000

Current page: 330 of 1226
Download datasheet (7Mb)

8. Pipelining

Rev.4.00 Oct. 10, 2008 Page 230 of 1122

REJ09B0370-0400

Functional

Category

Data transfer

instructions

Fixed-point

arithmetic

instructions

No.

32

33

34

35

36

37

38

39

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41

42

43

44

45

46

47

48

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61

62

Instruction

MOV.W

MOV.L

MOV.B

MOV.W

MOV.L

MOV.B

MOV.W

MOV.L

MOVCA.L R0,@Rn

MOVT

OCBI

OCBP

OCBWB

PREF

SWAP.B

SWAP.W

XTRCT

ADD

ADD

ADDC

ADDV

CMP/EQ

CMP/EQ

CMP/GE

CMP/GT

CMP/HI

CMP/HS

CMP/PL

CMP/PZ

CMP/STR Rm,Rn

DIV0S

R0,@(disp,Rn)

Rm,@(disp,Rn)

Rm,@(R0,Rn)

Rm,@(R0,Rn)

Rm,@(R0,Rn)

R0,@(disp,GBR)

R0,@(disp,GBR)

R0,@(disp,GBR)

Rn

@Rn

@Rn

@Rn

@Rn

Rm,Rn

Rm,Rn

Rm,Rn

Rm,Rn

#imm,Rn

Rm,Rn

Rm,Rn

#imm,R0

Rm,Rn

Rm,Rn

Rm,Rn

Rm,Rn

Rm,Rn

Rn

Rn

Rm,Rn

Instruc-

tion

Group

LS

LS

LS

LS

LS

LS

LS

LS

LS

EX

LS

LS

LS

LS

EX

EX

EX

EX

EX

EX

EX

MT

MT

MT

MT

MT

MT

MT

MT

MT

EX

Issue

Rate

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

Latency

1

1

1

1

1

1

1

1

3–7

1

1–2

1–5

1–5

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

Execu-

tion

Pattern Stage Start Cycles

#2

#2

#2

#2

#2

#3

#3

#3

#12

#1

#10

#11

#11

#2

#1

#1

#1

#1

#1

#1

#1

#1

#1

#1

#1

#1

#1

#1

#1

#1

#1

—

—

—

—

—

—

—

—

—

MA

—

MA

MA

MA

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

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4

—

4

4

4

—

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—

—

—

—

—

—

—

—

—

—

—

—

—

—

Lock

—

—

—

—

—

—

—

—

3–7

—

1–2

1–5

1–5

—

—

—

—

—

—

—

—

—

—

—

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