HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 622

MPU 1.5/3.3V 0K PB-FREE 256-QFP

HD6417751RF240V

Manufacturer Part Number
HD6417751RF240V
Description
MPU 1.5/3.3V 0K PB-FREE 256-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417751RF240V

Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-QFP Exposed Pad, 256-eQFP, 256-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417751RF240V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
14. Direct Memory Access Controller (DMAC)
On-Chip Peripheral Module Request Mode: In this mode a transfer is performed in response to
a transfer request signal (interrupt request signal) from an on-chip peripheral module. As shown in
table 14.5, there are seven transfer request signals: input capture interrupts from the timer unit
(TMU), and receive-data-full interrupts (RXI) and transmit-data-empty interrupts (TXI) from the
two serial communication interfaces (SCI, SCIF). If DMA transfer is enabled (DE = 1, DME = 1,
TE = 0, NMIF = 0, AE = 0), transfer starts when a transfer request signal is input.
The source of the transfer request does not have to be the data transfer source or destination.
However, when the transfer request is set to RXI (transfer request by SCI/SCIF receive-data-full
interrupt), the transfer source must be the SCI/SCIF's receive data register (SCRDR1/SCFRDR2).
When the transfer request is set to TXI (transfer request by SCI/SCIF transmit-data-empty
interrupt), the transfer destination must be the SCI/SCIF's transmit data register
(SCTDR1/SCFTDR2).
Table 14.5 Selecting On-Chip Peripheral Module Request Mode with RS Bits
RS3 RS2 RS1 RS0
1
Legend:
TMU: Timer unit
SCI:
SCIF: Serial communication interface with FIFO
Rev.4.00 Oct. 10, 2008 Page 522 of 1122
REJ09B0370-0400
0
1
Serial communication interface
0
1
0
1
0
1
0
1
0
1
0
DMAC Transfer
Request Source
SCI transmitter
SCI receiver
SCIF transmitter
SCIF receiver
TMU channel 2
TMU channel 2
TMU channel 2
DMAC Transfer
Request Signal
SCTDR1 (SCI
transmit-data-
empty transfer
request)
SCRDR1 (SCI
receive-data-full
transfer request)
SCFTDR2 (SCIF
transmit-data-
empty transfer
request)
SCFRDR2 (SCIF
receive-data-full
transfer request)
Input capture
occurrence
Input capture
occurrence
Input capture
occurrence
Transfer
Source
External*
SCRDR1
External*
SCFRDR2 External*
External*
External*
On-chip
peripheral
Transfer
Destination Bus Mode
SCTDR1
External*
SCFTDR2
External*
On-chip
peripheral
External*
Cycle steal
mode
Cycle steal
mode
Cycle steal
mode
Cycle steal
mode
Burst/cycle
steal mode
Burst/cycle
steal mode
Burst/cycle
steal mode

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