HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 860

MPU 1.5/3.3V 0K PB-FREE 256-QFP

HD6417751RF240V

Manufacturer Part Number
HD6417751RF240V
Description
MPU 1.5/3.3V 0K PB-FREE 256-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417751RF240V

Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-QFP Exposed Pad, 256-eQFP, 256-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417751RF240V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
18. I/O Ports
Bit 2n + 1 (n = 0–15)—Port Pull-Up Control (PBnPUP): Specifies whether each bit in the 16-
bit port A is to be pulled up with a built-in resistor. Pull-up is automatically turned off for a port
pin set to output by bit PBnIO.
Bit 2n + 1: PBnPUP
0
1
Bit 2n (n = 0–15)—Port I/O Control (PBnIO): Specifies whether each bit in the 16-bit port A is
an input or an output.
Bit 2n: PBnIO
0
1
18.2.2
Port data register A (PDTRA) is a 16-bit readable/writable register used as a data latch for each bit
in the 16-bit port A. When a bit is set as an output, the value written to the PDTRA register is
output from the external pin. When a value is read from the PDTRA register while a bit is set as an
input, the external pin value sampled on the external bus clock is read. When a bit is set as an
output, the value written to the PDTRA register is read.
PDTRA is not initialized by a power-on or manual reset, or in standby mode, and retains its
contents.
Rev.4.00 Oct. 10, 2008 Page 760 of 1122
REJ09B0370-0400
Initial value:
Initial value:
R/W:
R/W:
Port Data Register A (PDTRA)
Bit:
Bit:
PB15DT PB14DT PB13DT PB12DT PB11DT PB10DT
PB7DT
R/W
R/W
15
7
Description
Bit m (m = 0–15) of 16-bit port A is pulled up
Bit m (m = 0–15) of 16-bit port A is not pulled up
Description
Bit m (m = 0–15) of 16-bit port A is an input
Bit m (m = 0–15) of 16-bit port A is an output
PB6DT
R/W
R/W
14
6
PB5DT
R/W
R/W
13
5
PB4DT
R/W
R/W
12
4
PB3DT
R/W
R/W
11
3
PB2DT
R/W
R/W
10
2
PB9DT
PB1DT
R/W
R/W
9
1
(Initial value)
(Initial value)
PB8DT
PB0DT
R/W
R/W
8
0

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