HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 625
HD6417751RF240V
Manufacturer Part Number
HD6417751RF240V
Description
MPU 1.5/3.3V 0K PB-FREE 256-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417751RBP200DV.pdf
(1226 pages)
Specifications of HD6417751RF240V
Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-QFP Exposed Pad, 256-eQFP, 256-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417751RF240V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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1. Transfer requests are issued simultaneously for channels 0 and 3.
2. Since channel 0 has a higher priority level than channel 3, the channel 0 transfer is executed
3. A transfer request is issued for channel 1 during the channel 0 transfer (channels 1 and 3 are on
4. At the end of the channel 0 transfer, channel 0 shifts to the lowest priority level.
5. At this point, channel 1 has a higher priority level than channel 3, so the channel 1 transfer is
6. At the end of the channel 1 transfer, channel 1 shifts to the lowest priority level.
7. The channel 3 transfer is started.
8. At the end of the channel 3 transfer, the channel 3 and channel 2 priority levels are lowered,
first (channel 3 is on transfer standby).
transfer standby).
started (channel 3 is on transfer standby).
giving channel 3 the lowest priority.
Figure 14.4 Example of Changes in Priority Order in Round Robin Mode
Transfer request
1. Issued for channels 0
3. Issued for channel 1
and 3
Channel
waiting
3
1, 3
3
None
2. Start of channel 0
4. End of channel 0
5. Start of channel 1
6. End of channel 1
7. Start of channel 3
8. End of channel 3
DMAC operation
transfer
transfer
transfer
transfer
transfer
transfer
14. Direct Memory Access Controller (DMAC)
Rev.4.00 Oct. 10, 2008 Page 525 of 1122
Change of
priority order
Change of
priority order
Change of
priority order
Channel priority
0 > 1 > 2 > 3
1 > 2 > 3 > 0
2 > 3 > 0 > 1
0 > 1 > 2 > 3
order
REJ09B0370-0400
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