HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 308

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

7. Instruction Set
2. Incorrect data may be written to the operand cache when the following three conditions occur
3. The ITLB hit judgment may be incorrect when the following three conditions occur at the
4. Incorrect data may be written to an FPU-related register (FR0 to FR15, XF0 to XF15, FPSCR,
Note: The number of instructions following the instructions mentioned above that may be
Rev.4.00 Oct. 10, 2008 Page 208 of 1122
REJ09B0370-0400
b. A TRAPA instruction or undefined instruction code H'FFFD in a cache-enabled area (U0,
c. The four words of data following the TRAPA instruction or undefined instruction code
at the same time.
a. The operand cache is enabled (CCR.OCE = 1).
b. Undefined instruction code H'FFFD is executed.
c. The four words of data following the undefined instruction code H'FFFD mentioned in b.
same time. If an ITLB hit is erroneously judged to be a miss, ITLB re-registration is
performed. This can cause an ITLB multi-hit exception to occur.
a. The MMU is enabled (MMUCR.AT = 1).
b. A TRAPA instruction or undefined instruction code H'FFFD in a TLB conversion area
c. The four words of data following the TRAPA instruction or undefined instruction code
or FPUL) or to the MACH or MACL register when the following two conditions occur at the
same time.
a. A TRAPA instruction, SLEEP instruction, or undefined instruction code H'FFFD is
b. The eight words of data following the TRAPA instruction, SLEEP instruction, or undefined
P0, P1, or P3 area) is executed.
H'FFFD mentioned in b. contain code that can be interpreted as an instruction to access
(read or write) an address (H'F0000000 to H'F7FFFFFF) mapped to the internal cache or
internal TLB.
contain code that can be interpreted as an OCBI, OCBP, OCBWB, or TAS.B instruction
accessing an address (H'E0000000 to H'E3FFFFFF) mapped to the internal store queue.
(U0, P0, or P3 area) is executed.
H'FFFD mentioned in b. contain code that can be interpreted as an instruction to access
(read or write) an address (H'F0000000 to H'F7FFFFFF) mapped to the internal cache or
internal TLB.
executed
instruction code H'FFFD mentioned in a. contain H'Fxxx (an instruction with H'F as the
first four bits), excluding H'FFFD, and the code can be interpreted, in combination with
FPSCR.PR at that point, as an undefined instruction.
Example: Instruction H'FxxE (x: any hexadecimal digit) is defined here as undefined when
FPSCR.PR is set to 1.
affected by the problem is as follows: in the case of 1. to 3., the number of instructions
that can be executed in 2xIck, and in the case of 4., the number of instructions that can be
executed in 4xIck. The maximum number of instructions that can be executed in 2xIck or