HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 749

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Multiprocessor Serial Data Reception
1. Method for determining whether an interrupt generated during receive operation is a
2. Method for determining whether received data is ID or data
Serial
data
TDRE
TEND
multiprocessor interrupt
When an interrupt such as RXI occurs during receive operation using the on-chip SCI
multiprocessor communication function, check the state of the MPIE bit in the SCSCR1
register as part of the interrupt handling routine.
a. If the MPIE bit in the SCSCR1 register is set to 1
b. If the MPIE bit in the SCSCR1 register is cleared to 0
Do not use the MPB bit in the SCSSR1 register for software processing.
1
Ignore the received data.
Data with the multiprocessor bit (MPB) set to 0 and intended for another station was
received, and the RDRF bit in the SCSCR1 register was set to 1. Therefore, clear the
RDRF bit in the SCSCR1 register to 0.
A multiprocessor interrupt indicating that data (ID) with the multiprocessor bit (MPB) set
to 1 was received, or a receive data full interrupt (RXI) occurred when data with the
multiprocessor bit (MPB) set to 0 and intended for this station was received.
Figure 15.14 Example of SCI Transmit Operation (Example with 8-Bit Data,
Start
bit
0
D0 D1
One frame
Data
D7
Multi-
proces-
sor bit
MPBT bit cleared to 0, data
written to SCTDR1, and
TDRE flag cleared to 0 by
TEI interrupt handler
1
Multiprocessor Bit, One Stop Bit)
Stop
bit
1
Data written to SCTDR1
and TDRE flag cleared
to 0 by TXI interrupt
handler
Start
bit
0
D0 D1
Data
D7
Rev.4.00 Oct. 10, 2008 Page 649 of 1122
15. Serial Communication Interface (SCI)
Multi-
proces-
sor bit
0
Stop
bit
TXI interrupt
request
1
Start
bit
0
D0 D1
Data
D7
REJ09B0370-0400
Multi-
proces-
sor bit
TEI interrupt
request
0
Stop
bit
Idle state
(mark state)
1