HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 386
HD6417751RF240V
Manufacturer Part Number
HD6417751RF240V
Description
MPU 1.5/3.3V 0K PB-FREE 256-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417751RBP200DV.pdf
(1226 pages)
Specifications of HD6417751RF240V
Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-QFP Exposed Pad, 256-eQFP, 256-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417751RF240V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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10. Clock Oscillation Circuits
6. When re-setting WTCNT immediately after modifying the frequency control register
10.9.3
1. Set the WT/IT bit in the WTCSR register to 1, select the type of reset with the RSTS bit, and
2. When the TME bit in the WTCSR register is set to 1, the count starts in watchdog timer mode.
3. During operation in watchdog timer mode, write H'00 to the counter periodically so that it does
4. When the counter overflows, the WDT sets the WOVF flag in the WTCSR register to 1, and
10.9.4
When the WDT is operating in interval timer mode, an interval timer interrupt is generated each
time the counter overflows. This enables interrupts to be generated at fixed intervals.
1. Clear the WT/IT bit in the WTCSR register to 0, select the count clock with bits CKS2–CKS0,
2. When the TME bit in the WTCSR register is set to 1, the count starts in interval timer mode.
3. When the counter overflows, the WDT sets the IOVF flag in the WTCSR register to 1, and
Rev.4.00 Oct. 10, 2008 Page 286 of 1122
REJ09B0370-0400
the count clock with bits CKS2–CKS0, and set the initial value in the WTCNT counter.
not overflow.
generates a reset of the type specified by the RSTS bit. The counter then continues counting.
and set the initial value in the WTCNT counter.
sends an interval timer interrupt request to INTC. The counter continues counting.
(FRQCR), first read the counter and confirm that its value is as described in step 5 above.
Using Watchdog Timer Mode
Using Interval Timer Mode
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