HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 1033
HD6417751RF240V
Manufacturer Part Number
HD6417751RF240V
Description
MPU 1.5/3.3V 0K PB-FREE 256-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417751RBP200DV.pdf
(1226 pages)
Specifications of HD6417751RF240V
Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-QFP Exposed Pad, 256-eQFP, 256-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417751RF240V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Configuration Register Access: The configuration register of external PCI devices can be
accessed when the PCIC is operating as the host device. The PIO address register (PCIPAR) and
PIO data register (PCIPDR) are used to generate a configuration read/write transfer for accessing
the configuration register.
The PCIC supports the configuration mechanism stipulated in the PCI local bus spec.
First, specify in the PCIPAR the address of the configuration register of the external PCI device to
be accessed. See section 22.2, PCIC Register Descriptions, for how to set the PCIPAR.
Next, read data from the PCIPDR or write data to the PCIPDR. Only longword (32-bit) access of
the PCIPDR is supported.
Special Cycle Generation: When the PCIC operates as the host device, a special cycle is
generated by setting H'8000FF00 in the PCIPAR and writing to the PCIPDR.
Reset Output: When the PCIC is operating as the host device, PCIRST can be used to reset the
PCI bus. See section 22.5, Resetting, for details of PCIRST.
Clock Output: When the PCIC is operating as the host device and the bus clock (CKIO pin) is
selected as the PCI bus clock, not only does the PCIC's PCI bus clock operate using the CKIO
clock but the CKIO clock can also be used as the PCI bus clock. Thus, there is no requirement for
an external PCI clock oscillation circuit.
When the PCIC is operating as the host device, the PCIC performs the PCI bus parking (bus
drive when not in use).
When 3 or fewer master devices are connected, set the level of the unused pins of PCIREQ
[4:1] high.
In non-host mode, the PCI bus arbitration function of the PCIC is disabled. PCI bus arbitration
is performed according to the specifications of the connected PCI bus arbiter. For details, see
section 22.3.6, PCI Bus Arbitration in Non-host Mode.
1.
2.
3.
4.
Initial order of priority
(transfer by device 1)
Order of priority after transfer
(transfer by PCIC)
Order of priority after transfer
(transfer by device 3)
Order of priority after transfer
PCIC > device 1 > device 2 > device 3 > device 4
PCIC > device 2 > device 3 > device 4 > device 1
device 2 > device 3 > device 4 > device 1 > PCIC
device 2 > device 4 > device 1 > PCIC > device 3
Rev.4.00 Oct. 10, 2008 Page 933 of 1122
22. PCI Controller (PCIC)
REJ09B0370-0400
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