HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 1010

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

22. PCI Controller (PCIC)
22.2.31 PCI DMA Control Register [3:0] (PCIDCR [3:0])
Note: Cleared by writing WC:1. (Writing of 0 is ignored.)
The DMA transfer control register [3:0] (PCIDCR [3:0]) specifies the operating mode of the
respective channels and the method of transfer, etc. This 32-bit read/write register can be accessed
from the PP bus and PCI bus.
The PCIDCR register is initialized to H'00000000 at a power-on reset and software reset.
Writing 1 to bit 0 (DMASTRT) starts DMA transfer. Always re-set the value in this register before
starting a new DMA transfer after completion of a DMA transfer.
When setting the DMASTOP bit, do not write 1 to the DMASTART bit. Also, write the same
setting at the start of transfer to the DMAIM, DMAIS, LAHOLD, IOSEL and DIR bits.
Example: Starting transfer with PCIDCR = H'00000085
If DMA is forcibly terminated with a value other than the setting used in the transfer being
performed, data accuracy is not guaranteed.
Rev.4.00 Oct. 10, 2008 Page 910 of 1122
REJ09B0370-0400
PP Bus-R/W:
PP Bus-R/W:
PP Bus-R/W:
Initial value:
Initial value:
Initial value:
PCI-R/W:
PCI-R/W:
PCI-R/W:
Bit:
Bit:
Bit:
Forced DMA termination PCIDCR = H'00000086
DMAIM
R/W
R/W
31
15
—
—
R
R
R
R
0
0
7
0
DMAIS
R/WC
R/WC
30
14
—
—
R
R
R
R
0
6
0
0
LAHOLD
R/W
R/W
29
13
—
—
R
R
R
R
0
0
5
0
. . .
. . .
. . .
. . .
. . .
12
—
—
R
R
R
R
0
4
0
IOSEL0
R/W
R/W
19
11
—
—
R
R
R
R
0
0
3
0
ALNMD10 ALMMD9
R/W
R/W
R/W
R/W
DIR
18
10
—
R
R
0
0
2
0
DMASTOP DMASTRT
R/W
R/W
R/W
R/W
17
—
R
R
0
9
0
1
0
DMAST
R/W
R/W
16
—
R
R
R
R
0
8
0
0
0