HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 635

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Since channel 1 is in burst mode (in the case of edge sensing) regardless of whether fixed mode or
round robin mode is set for the priority order, the bus is not released to the CPU until channel 1
transfer ends.
Note: When channel 1 is in level-sensing burst mode with the settings shown in figure 14.11, the
14.3.5
Number of States in Bus Cycle: The number of states in the bus cycle when the DMAC is the
bus master is controlled by the bus state controller (BSC) just as it is when the CPU is the bus
master. See section 13, Bus State Controller (BSC), for details.
DREQ Pin Sampling Timing: In external request mode, the DREQ pin is sampled at the rising
edge of CKIO clock pulses. When DREQ input is detected, a DMAC bus cycle is generated and
DMA transfer executed after four CKIO cycles at the earliest.
With DREQ falling edge detection, as the signal passes via an asynchronous circuit the DMAC
recognizes DREQ two cycles (CKIO) later (one cycle (CKIO) later in the case of low level
detection).
The second and subsequent DREQ sampling operations are performed one cycle after the start of
the first DMAC transfer bus cycle (in the case of single address mode).
DRAK is output for one cycle only, once each time DREQ is detected, regardless of the transfer
mode or DREQ detection method. In the case of burst mode edge detection, DREQ is sampled in
the first cycle only, and so DRAK is output in the first cycle only .
Notes:
Priority system: Round robin mode
Channel 0:
Channel 1:
CPU
CPU
bus is passed to the CPU during a break in requests.
Number of Bus Cycle States and DREQ Pin Sampling Timing
Figure 14.11 Bus Handling with Two DMAC Channels Operating
DMAC CH1
DMAC channel 1
burst mode
Cycle steal mode
Burst mode (edge-sensing)
DMAC CH1
DMAC CH0
CH0
DMAC channel 0 and
channel 1 round robin
mode
DMAC CH1
CH1
14. Direct Memory Access Controller (DMAC)
Rev.4.00 Oct. 10, 2008 Page 535 of 1122
DMAC CH0
CH0
DMAC CH1
DMAC channel 1
burst mode
DMAC CH1
REJ09B0370-0400
CPU
CPU