HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 161

MPU 1.5/3.3V 0K PB-FREE 256-QFP

HD6417751RF240V

Manufacturer Part Number
HD6417751RF240V
Description
MPU 1.5/3.3V 0K PB-FREE 256-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417751RF240V

Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-QFP Exposed Pad, 256-eQFP, 256-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417751RF240V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
branches to the start address of the user-coded exception service routine found from the sum of the
contents of the vector base address and the vector offset. See section 5, Exceptions, for more
information on resets, general exceptions, and interrupts.
Program Execution State: In this state the CPU executes program instructions in sequence.
Power-Down State: In the power-down state, CPU operation halts and power consumption is
reduced. The power-down state is entered by executing a SLEEP instruction. There are three
modes in the power-down state: sleep mode, deep sleep mode, and standby mode. For details, see
section 9, Power-Down Modes.
Bus-Released State: In this state the CPU has released the bus to a device that requested it.
Transitions between the states are shown in figure 2.6.
Interrupt
From any state when
RESET = 0
Bus request
Bus-released state
Figure 2.6 Processor State Transitions
Bus request
clearance
Power-on reset state
Bus request
Sleep mode
SLEEP instruction
with STBY bit
cleared
Bus
request
RESET = 1
Bus request
Bus request
clearance
clearance
RESET = 1 and MRESET = 0
Exception-handling state
Program execution state
Exception
interrupt
RESET = 0
End of exception
transition
processing
Rev.4.00 Oct. 10, 2008 Page 61 of 1122
RESET = 1,
MRESET = 1
SLEEP instruction
with STBY bit set
Manual reset state
Standby mode
Power-down state
Reset state
2. Programming Model
REJ09B0370-0400
Interrupt

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