HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 89

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Figure 23.35 DRAM Bus Cycles (1) RCD [1:0] = 00, AnW [2:0] = 000, TPC [2:0] = 001 (2)
Figure 23.36 DRAM Bus Cycle (EDO Mode, RCD [1:0] = 00, AnW [2:0] = 000,
Figure 23.37 DRAM Bus Cycle (EDO Mode, RCD [1:0] = 00, AnW [2:0] = 000,
Figure 23.38 DRAM Burst Bus Cycle (EDO Mode, RCD [1:0] = 01, AnW [2:0] = 001,
Figure 23.39 DRAM Burst Bus Cycle (EDO Mode, RCD [1:0] = 01, AnW [2:0] = 001,
Figure 23.40 DRAM Burst Bus Cycle: RAS Down Mode State
Figure 23.41 DRAM Burst Bus Cycle: RAS Down Mode Continuation
Figure 23.42 DRAM Burst Bus Cycle (Fast Page Mode, RCD [1:0] = 00,
Figure 23.43 DRAM Burst Bus Cycle (Fast Page Mode, RCD [1:0] = 01,
Figure 23.44 DRAM Burst Bus Cycle (Fast Page Mode, RCD [1:0] = 01, AnW [2:0] = 001,
Figure 23.45 DRAM Burst Bus Cycle: RAS Down Mode State (Fast Page Mode,
Figure 23.46 DRAM Burst Bus Cycle: RAS Down Mode Continuation
Figure 23.47 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh
Figure 23.48 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh
Figure 23.49 DRAM Bus Cycle: DRAM Self-Refresh (TRC [2:0] = 001) ............................. 1051
Figure 23.50 PCMCIA Memory Bus Cycle (1) TED [2:0] = 000, TEH [2:0] = 000,
Figure 23.51 PCMCIA I/O Bus Cycle (1) TED [2:0] = 000, TEH [2:0] = 000,
Figure 23.52 PCMCIA I/O Bus Cycle (TED [2:0] = 001, TEH [2:0] = 001,
Figure 23.53 MPX Basic Bus Cycle: Read (1) 1st Data (One Internal Wait) (2) 1st Data
RCD [1:0] = 01, AnW [2:0] = 001, TPC [2:0] = 010 ......................................... 1037
TRC [2:0] = 001)................................................................................................ 1038
TPC [2:0] = 001) ................................................................................................ 1039
TPC [2:0] = 001) ................................................................................................ 1040
TPC [2:0] = 001, 2-Cycle CAS Negate Pulse Width) ........................................ 1041
(EDO Mode, RCD [1:0] = 00, AnW [2:0] = 000) .............................................. 1042
(EDO Mode, RCD [1:0] = 00, AnW [2:0] = 000) .............................................. 1043
AnW [2:0] = 000, TPC [2:0] = 001)................................................................... 1044
AnW [2:0] = 001, TPC [2:0] = 001)................................................................... 1045
TPC [2:0] = 001, 2-Cycle CAS Negate Pulse Width) ........................................ 1046
RCD [1:0] = 00, AnW [2:0] = 000).................................................................... 1047
(Fast Page Mode, RCD [1:0] = 00, AnW [2:0] = 000) ....................................... 1048
(TRAS [2:0] = 000, TRC [2:0] = 001) ............................................................... 1049
(TRAS [2:0] = 001, TRC [2:0] = 001) ............................................................... 1050
No Wait (2) TED [2:0] = 001, TEH [2:0] = 001, One Internal Wait + One
External Wait...................................................................................................... 1052
No Wait (2) TED [2:0] = 001, TEH [2:0] = 001, One Internal Wait +
One External Wait .............................................................................................. 1053
One Internal Wait, Bus Sizing) .......................................................................... 1054
(One Internal Wait + One External Wait) .......................................................... 1055
Rev.4.00 Oct. 10, 2008 Page lxxxvii of xcviii
REJ09B0370-0400