HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 814

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

16. Serial Communication Interface with FIFO (SCIF)
Table 16.6 SCIF Interrupt Sources
Interrupt
Source
ERI
RXI
BRI
TXI
See section 5, Exceptions, for priorities and the relationship with non-SCIF interrupts.
16.5
Note the following when using the SCIF.
SCFTDR2 Writing and the TDFE Flag: The TDFE flag in the serial status register (SCFSR2) is
set when the number of transmit data bytes written in the transmit FIFO data register (SCFTDR2)
has fallen to or below the transmit trigger number set by bits TTRG1 and TTRG0 in the FIFO
control register (SCFCR2). After TDFE is set, transmit data up to the number of empty bytes in
SCFTDR2 can be written, allowing efficient continuous transmission.
However, if the number of data bytes written in SCFTDR2 is equal to or less than the transmit
trigger number, the TDFE flag will be set to 1 again after being read as 1 and cleared to 0. TDFE
clearing should therefore be carried out when SCFTDR2 contains more than the transmit trigger
number of transmit data bytes.
data count register (SCFDR2).
SCFRDR2 Reading and the RDF Flag: The RDF flag in the serial status register (SCFSR2) is
set when the number of receive data bytes in the receive FIFO data register (SCFRDR2) has
become equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in the
FIFO control register (SCFCR2). After RDF is set, receive data equivalent to the trigger number
can be read from SCFRDR2, allowing efficient continuous reception.
However, if the number of data bytes in SCFRDR2 is equal to or greater than the trigger number,
the RDF flag will be set to 1 again if it is cleared to 0. RDF should therefore be cleared to 0 after
being read as 1 after all the receive data has been read.
Rev.4.00 Oct. 10, 2008 Page 714 of 1122
REJ09B0370-0400
The number of transmit data bytes in SCFTDR2 can be found from the upper 8 bits of the FIFO
Usage Notes
Description
Interrupt initiated by receive error flag (ER)
Interrupt initiated by receive FIFO data full flag
(RDF) or receive data ready flag (DR)
Interrupt initiated by break flag (BRK) or overrun
error flag (ORER)
Interrupt initiated by transmit FIFO data empty
flag (TDFE)
DMAC
Activation
Not possible
Possible
Not possible
Possible
Priority on
Reset Release
High
Low