HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 171

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

3.3
3.3.1
The SH-4 supports a 32-bit physical address space, and can access a 4-Gbyte address space. When
the MMUCR.AT bit is cleared to 0 and the MMU is disabled, the address space is this physical
address space. The physical address space is divided into a number of areas, as shown in figure
3.3. The physical address space is permanently mapped onto 29-bit external memory space; this
correspondence can be implemented by ignoring the upper 3 bits of the physical address space
addresses. In privileged mode, the 4-Gbyte space from the P0 area to the P4 area can be accessed.
In user mode, a 2-Gbyte space in the U0 area can be accessed. Accessing the P1 to P4 areas
(except the store queue area) in user mode will cause an address error.
When performing access from the CPU to a PCMCIA interface area in the SH-4, access is always
performed using the values of the SA and TC bits set in the PTEA register. Access to a PCMCIA
interface area by the DMAC is always performed using the DMAC's CHCRn.SSAn,
H'0000 0000
H'8000 0000
H'A000 0000
H'C000 0000
H'E000 0000
H'FFFF FFFF
Address Space
Physical Address Space
Privileged mode
Non-cacheable
Non-cacheable
Figure 3.3 Physical Address Space (MMUCR.AT = 0)
Cacheable
Cacheable
Cacheable
P0 area
P1 area
P2 area
P3 area
P4 area
memory space
External
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
Rev.4.00 Oct. 10, 2008 Page 71 of 1122
3. Memory Management Unit (MMU)
Store queue area
Address error
Address error
User mode
Cacheable
U0 area
REJ09B0370-0400
H'0000 0000
H'8000 0000
H'E000 0000
H'E400 0000
H'FFFF FFFF