HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 46

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Rev.4.00 Oct. 10, 2008 Page xliv of xcviii
REJ09B0370-0400
Item
22.9.1 Power
Management Overview
22.9.2 Stopping the
Clock
Table 22.14 Method of
Stopping Clock per
Operating Mode
22.12 Usage Notes
Page
973
974, 975 Table amended
977 to
980
Revision (See Manual for Details)
Description amended
Of the power management interrupts, the power state D3
(PWRST_D3) interrupt detects a transition from the power state
D0 to D3, while power state D0 (PWRST_D0) interrupt detects
a transition from the power state D3 to D0.
Newly added
Clock
operating
status
Transition/
Recovery
Transition/
Recovery
Standby
Normal
operation/
sleep
Deep sleep
Standby
Deep sleep
Bck
Pck
PCICLK
Bck
Pck
PCICLK
Bck
Pck
PCICLK
Transition Sleep
Recovery
1
Recovery
2
Transition Standby
Recovery
1
Recovery
2
Normal
Normal
Stopped
Normal
Stopped
Stopped
LSI (Other
than PCIC)
operation
operation
Not used
operation
Not used
Not used
command
Not used
NMI, IRL,
and
RESET
on-chip
peripheral
interrupt
command
Not used
NMI, IRL,
and
RESET
on-chip
peripheral
interrupt
NMI, IRL,
RESET + Bck
restarted
from LSI
Standby
command
PME
interrupt
(connected
to IRL)
NMI, IRL,
and RESET
PCICLK
Operation
Normal
operation
Normal
operation
Normal
operation
Stopped
Normal
operation
Normal
operation
Stopped
Stopped
Stopped
Bck stopped
from LSI
PME
interrupt
(connected
to IRL) + Bck
restarted
from LSI
Master
CKIO
Operation
Normal
operation
Normal
operation
Not used
Stopped
Normal
operation
Not used
Stopped
Stopped
Bck and
PCICLK
stopped from
LSI
PME interrupt
(connected to
IRL) + Bck and
PCICLK
restarted from
LSI
NMI, IRL,
RESET + Bck
and PCICLK
restarted from
LSI
PCICLK
stopped from
LSI + standby
command
PME interrupt
(connected to
IRL) + PCICLK
restarted from
LSI
NMI, IRL,
RESET +
PCICLK
restarted from
LSI
Not used
PCIC
Slave
PCICLK
Operation
Normal
operation
Normal
operation
Normal
operation
Stopped
Normal
operation
Normal
operation
Stopped
Stopped
Stopped
PCI command
+ interrupt
(PCIC → LSI)
+ Bck restarted
from LSI
PCI command
+ interrupt
(PCIC → LSI)
+ Bck restarted
from LSI
NMI, IRL,
RESET + Bck
restarted from
LSI + wait for
PCI command
(recovery)
PCI command
+ interrupt
(PCIC → LSI)
+ standby
command
Power-on reset
NMI, IRL,
RESET + wait
for PCI
command
(recovery)