HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 199

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

1. UTLB data array 1 read
2. UTLB data array 1 write
3.7.6
UTLB data array 2 is allocated to addresses H'F780 0000 to H'F7FF FFFF in the P4 area. A data
array access requires a 32-bit address field specification (when reading or writing) and a 32-bit
data field specification (when writing). Information for selecting the entry to be accessed is
specified in the address field, and SA and TC to be written to data array 2 are specified in the data
field.
In the address field, bits [31:23] have the value H'F78 indicating UTLB data array 2, and the entry
is selected by bits [13:8].
In the data field, TC is indicated by bit [3], and SA by bits [2:0].
The following two kinds of operation can be used on UTLB data array 2:
1. UTLB data array 2 read
Address field
Legend:
PPN:
V:
E:
SZ:
D:
PPN, V, SZ, PR, C, D, SH, and WT are read into the data field from the UTLB entry
corresponding to the entry set in the address field.
PPN, V, SZ, PR, C, D, SH, and WT specified in the data field are written to the UTLB entry
corresponding to the entry set in the address field.
SA and TC are read into the data field from the UTLB entry corresponding to the entry set in
the address field.
Data field
Physical page number
Validity bit
Entry
Page size bits
Dirty bit
UTLB Data Array 2
31
31
1 1 1 1 0 1 1 1 0
30 29 28
Figure 3.17 Memory-Mapped UTLB Data Array 1
24
PR:
C:
SH:
WT:
23
:
Protection key data
Cacheability bit
Share status bit
Write-through bit
Reserved bits (0 write value, undefined read value)
PPN
Rev.4.00 Oct. 10, 2008 Page 99 of 1122
14 13
3. Memory Management Unit (MMU)
E
10 9 8 7
8 7
V
6 5
REJ09B0370-0400
PR
SZ
4 3
C
SH WT
2 1 0
D
0