HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 718

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

15. Serial Communication Interface (SCI)
Bit 2—Transmit End (TEND): Indicates that there is no valid data in SCTDR1 when the last bit
of the transmit character is sent, and transmission has been ended.
The TEND flag is read-only and cannot be modified.
Bit 2: TEND
0
1
Bit 1—Multiprocessor Bit (MPB): This bit is read-only and cannot be written to. The read value
is undefined.
Note: This bit is prepared for storing a multi-processor bit in the received data when the receipt
Bit 0—Multiprocessor Bit Transfer (MPBT): When transmission is performed using a
multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to
the transmit data.
The MPBT bit setting is invalid in synchronous mode, when a multiprocessor format is not used,
and when the operation is not transmission.
Unlike transmit data, the MPBT bit is not double-buffered, so it is necessary to check whether
transmission has been completed before changing its value.
Bit 0: MPBT
0
1
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REJ09B0370-0400
is carried out with a multi-processor format in asynchronous mode, however, this does not
function correctly in this LSI. Do not use the read value from this bit.
Description
Transmission is in progress
[Clearing conditions]
•
•
Transmission has been ended
[Setting conditions]
•
•
•
Description
Data with a 0 multiprocessor bit is transmitted
Data with a 1 multiprocessor bit is transmitted
When 0 is written to TDRE after reading TDRE = 1
When data is written to SCTDR1 by the DMAC
Power-on reset, manual reset, standby mode, or module standby
When the TE bit in SCSCR1 is 0
When TDRE = 1 on transmission of the last bit of a 1-byte serial transmit
character
(Initial value)
(Initial value)