HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 777

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

16.2.5
SCSMR2 is a 16-bit register used to set the SCIF's serial transfer format and select the baud rate
generator clock source.
SCSMR2 can be read or written to by the CPU at all times.
SCSMR2 is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in
standby mode or in the module standby state.
Bits 15 to 7—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 6—Character Length (CHR): Selects 7 or 8 bits as the asynchronous mode data length.
Bit 6: CHR
0
1
Note:
Bit 5—Parity Enable (PE): Selects whether or not parity bit addition is performed in
transmission, and parity bit checking in reception.
Bit 5: PE
0
1
Note:
Initial value:
Initial value:
*
*
R/W:
R/W:
Serial Mode Register (SCSMR2)
Bit:
Bit:
When 7-bit data is selected, the MSB (bit 7) of SCFTDR2 is not transmitted.
When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to
transmit data before transmission. In reception, the parity bit is checked for the parity
(even or odd) specified by the O/E bit.
15
—
—
R
R
0
7
0
Description
8-bit data
7-bit data*
Description
Parity bit addition and checking disabled
Parity bit addition and checking enabled*
CHR
R/W
14
—
R
0
6
0
R/W
PE
13
—
R
0
0
5
16. Serial Communication Interface with FIFO (SCIF)
R/W
O/E
12
—
R
0
4
0
Rev.4.00 Oct. 10, 2008 Page 677 of 1122
STOP
R/W
11
—
R
0
3
0
10
—
—
R
R
0
2
0
REJ09B0370-0400
CKS1
R/W
—
R
9
0
1
0
(Initial value)
(Initial value)
CKS0
R/W
—
R
8
0
0
0