HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 927

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

21.2
21.2.1
The instruction register (SDIR) is a 16-bit register that can only be read by the CPU. In the initial
state, bypass mode is set. The value (command) is set from the serial input pin (TDI). SDIR is
initialized by the TRST pin or in the TAP Test-Logic-Reset state. When this register is written to
from the H-UDI, writing is possible regardless of the CPU mode. Operation is undefined if a
reserved command is set in this register.
Bits 15 to 8—Test Instruction Bits (TI7–TI0)
Bit 15:
TI7
0
0
0
0
1
1
Other than above
Bits 7 to 0—Reserved: These bits are always read as 1, and should only be written with 1.
Initial value:
Initial value:
R/W:
R/W:
Bit 14:
TI6
0
0
1
1
0
1
Register Descriptions
Instruction Register (SDIR)
Bit:
Bit:
Bit 13:
TI5
0
0
1
1
1
1
TI7
15
—
R
R
1
7
1
Bit 12:
TI4
0
0
0
1
—
1
TI6
14
—
R
R
1
6
1
Bit 11:
TI3
0
0
—
—
—
1
TI5
13
—
R
R
1
1
5
Bit 10:
TI2
0
1
—
—
—
1
21. High-performance User Debug Interface (H-UDI)
TI4
12
—
R
R
1
4
1
Bit 9:
TI1
0
0
—
—
—
1
Rev.4.00 Oct. 10, 2008 Page 827 of 1122
TI3
11
—
Bit 8:
TI0
0
0
—
—
—
1
R
R
1
3
1
Description
EXTEST
SAMPLE/PRELOAD
H-UDI reset negate
H-UDI reset assert
H-UDI interrupt
Bypass mode (Initial value)
Reserved
TI2
10
—
R
R
1
2
1
REJ09B0370-0400
TI1
—
R
R
9
1
1
1
TI0
—
R
R
8
1
0
1