HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 353

MPU 1.5/3.3V 0K PB-FREE 256-QFP

HD6417751RF240V

Manufacturer Part Number
HD6417751RF240V
Description
MPU 1.5/3.3V 0K PB-FREE 256-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417751RF240V

Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-QFP Exposed Pad, 256-eQFP, 256-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417751RF240V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
The module standby function is not exited by means of a power-on reset via the RESET pin or a
power-on reset caused by watchdog timer overflow.
9.8
9.8.1
Setting the CA pin level low effects a transition to hardware standby mode. In this mode, all
modules other than the RTC stop, as in the standby mode selected using the SLEEP command.
Hardware standby mode differs from standby mode as follows:
1. Interrupts and manual resets are not available;
2. All output pins other than the STATUS pin are in the high-impedance state and the pull-up
3. On the SH7751, the RTC continues to operate even when no power is supplied to power pins
The status of the STATUS pin is determined by the STHZ bit of STBCR2. See section D, Pin
Functions, for details of output pin states.
Operation when a low-level is input to the CA pin when in the standby mode depends on the CPG
status, as follows:
1. In standby mode
2. When WDT is operating when standby mode is exited by interrupt
Note that the level of the CA pin must be kept low while in hardware standby mode.
9.8.2
Hardware standby mode can only be cancelled by a power-on reset. Driving the CA pin high when
the RESET pin is being driven low causes clock oscillation to start. At this point, maintain the
RESET pin at low level until clock oscillation stabilizes. The CPU will start power-on reset
processing if the RESET pin is driven high. Hardware standby mode cannot be cancelled by an
interrupt or a manual reset.
resistance is off.
other than the RTC power supply pin.
The clock remains stopped and a transition is made to the hardware standby state.
Interrupts and manual resets are disabled, but the output pins remain in the same state as in
standby mode.
Standby mode is momentarily exited, the CPU restarts, and then a transition is made to
hardware standby mode.
Hardware Standby Mode
Transition to Hardware Standby Mode
Exit from Hardware Standby Mode
Rev.4.00 Oct. 10, 2008 Page 253 of 1122
9. Power-Down Modes
REJ09B0370-0400

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