HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 1028

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

22. PCI Controller (PCIC)
Always write to this register before accessing the PCI configuration space. Always read/write to
this register after setting the value in the PIO address register (PCIPAR).
The configuration cycle on the PCI bus can be generated by reading/writing to this register.
Bits 31 to 0—PIO Configuration Data (PPDA31 to 0): Read/write register for configuration
data in PIO transfers.
The configuration cycle on the PCI bus can be generated by reading/writing to this register.
22.3
22.3.1
The external mode pins (MD9 and MD10) select whether the PCIC operates as the host on the PCI
bus and also select the bus clock for the PCI bus. The mode selection signals input via the external
mode pins are fetched on negation of a power-on reset.
Table 22.8 Operating Modes
MD9
1
Note: In PCIC-disabled mode, do not attempt to access the PCIC local registers.
In this section, the clock resulting from the above mode switching is known as the PCI bus clock.
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REJ09B0370-0400
0
Description of Operation
Operating Modes
MD10
0
1
0
1
Operating Modes
The PCIC host functions are disabled (non-host) and
the input clock from the PCICLK pin is selected as the
clock for the PCI bus
PCIC-disabled mode. In this mode, PCIC operation is
disabled
The PCIC host functions are enabled and the external
input via the PCICLK pin is the operating clock for the
PCI bus
The PCIC host functions are enabled and this LSI bus
clock (feedback input clock from CKIO pin) is the
operating clock for the PCI bus