HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 912

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

20. User Break Controller (UBC)
20.3.6
1. Instruction access with post-execution condition, or operand access
2. Instruction access with pre-execution condition
20.3.7
1. When instruction access (pre-execution) is set as a break condition, the program counter (PC)
2. When instruction access (post-execution) is set as a break condition, the program counter (PC)
3. When an instruction access (post-execution) break condition is set for a delayed branch
Rev.4.00 Oct. 10, 2008 Page 812 of 1122
REJ09B0370-0400
The flag is set when execution of the instruction that causes the break is completed. As an
exception to this, however, in the case of an instruction with more than one operand access the
flag may be set on detection of the match condition alone, without waiting for execution of the
instruction to be completed.
Example 1:
100 BT L200 (branch performed)
102 Instruction (operand access break on channel A) → flag not set
Example 2:
110 FADD (FPU exception)
112 Instruction (operand access break on channel A) → flag not set
The flag is set when the break match condition is detected.
Example 1:
110 Instruction (pre-execution break on channel A) → flag set
112 Instruction (pre-execution break on channel B) → flag not set
Example 2:
110 Instruction (pre-execution break on channel B, instruction access TLB miss) → flag set
value saved to SPC in user break interrupt handling is the address of the instruction at which
the break condition match occurred. In this case, a user break interrupt is generated and the
fetched instruction is not executed.
value saved to SPC in user break interrupt handling is the address of the instruction to be
executed after the instruction at which the break condition match occurred. In this case, the
fetched instruction is executed, and a user break interrupt is generated before execution of the
next instruction.
instruction, the delay slot instruction is executed and a user break is effected before execution
of the instruction at the branch destination (when the branch is made) or the instruction two
instructions ahead of the branch instruction (when the branch is not made). In this case, the PC
Condition Match Flag Setting
Program Counter (PC) Value Saved