HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 352

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

9. Power-Down Modes
Bit
CSTP2
CSTP1
CSTP0
MSTP6
MSTP5
MSTP4
MSTP3
MSTP2
MSTP1
MSTP0
Notes: 1. The register initialized is the same as in standby mode, but initialization is not
9.7.2
In the case of the standby control register and standby control register 2, the module standby
function is exited by writing 0 to the MSTP6–MSTP0 bits. In the case of clock stop register 00,
the module standby function is exited by writing 1 to the corresponding bit in clock stop clear
register 00.
Rev.4.00 Oct. 10, 2008 Page 252 of 1122
REJ09B0370-0400
2. The counter operates when the START bit in RCR2 is 1 (see section 11, Realtime
3. For details, see section 20.6, User Break Controller Stop Function.
4. Terminate DMA transfers prior to making the transition to module standby mode. If you
Exit from Module Standby Function
performed if the RTC clock is not in use (see section 12, Timer Unit (TMU)).
Clock (RTC)).
make a transition to module standby mode while DMA transfers are in progress, the
results of those transfers cannot be guaranteed.
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
Peripheral clock is supplied to PCIC
Peripheral clock supply to PCIC is stopped
Peripheral clock is supplied to TMU channels 3 and 4
Peripheral clock supply to TMU channels 3 and 4 is stopped
INTC detects PCIC and TMU channel 3 and 4 interrupts
INTC does not detect PCIC and TMU channel 3 and 4 interrupts
SQ operates
Clock supplied to SQ is stopped
UBC operates
Clock supplied to UBC is stopped*
DMAC operates
Clock supplied to DMAC is stopped*
SCIF operates
Clock supplied to SCIF is stopped
TMU operates
Clock supplied to TMU is stopped, and register is initialized*
RTC operates
Clock supplied to RTC is stopped*
SCI operates
Clock supplied to SCI is stopped
2
3
4
1