HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 783

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit 7—Receive Error (ER): Indicates that a framing error or parity error occurred during
reception.*
Note: * The ER flag is not affected and retains its previous state when the RE bit in SCSCR2 is
Bit 7: ER
0
1
Note:
*
cleared to 0. When a receive error occurs, the receive data is still transferred to
SCFRDR2, and reception continues.
The FER and PER bits in SCFSR2 can be used to determine whether there is a receive
error in the data read from SCFRDR2.
In 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit
is not checked.
Description
No framing error or parity error occurred during reception
[Clearing conditions]
•
•
A framing error or parity error occurred during reception
[Setting conditions]
•
•
Power-on reset or manual reset
When 0 is written to ER after reading ER = 1
When the SCIF checks whether the stop bit at the end of the receive
data is 1 when reception ends, and the stop bit is 0*
When, in reception, the number of 1-bits in the receive data plus the
parity bit does not match the parity setting (even or odd) specified by the
O/E bit in SCSMR2
16. Serial Communication Interface with FIFO (SCIF)
Rev.4.00 Oct. 10, 2008 Page 683 of 1122
REJ09B0370-0400
(Initial value)