HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 23

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Item
12.2.7 Input Capture
Register 2 (TCPR2)
12.4 Interrupts
12.5.4 External Clock
Frequency
13.1.4 Register
Configuration
Table 13.2 BSC
Registers
13.1.6 PCMCIA
Support
Table 13.5 PCMCIA
Support Interfaces
13.2.3 Bus Control
Register 3 (BCR3)
(SH7751R Only)
13.2.7 Wait Control
Register 3 (WCR3)
Page
326
332
333
340
347
359
375
Revision (See Manual for Details)
Title amended
Description amended
There are six TMU interrupt sources, comprising underflow
interrupts and the input capture interrupt (when the input
capture function is used). Underflow interrupts are generated
on channels 0 to 4, and input capture interrupts on channel 2
only.
Description amended
Ensure that the external clock frequency for any channel does
not exceed Pck/8.
Table amended
Name
Bus control register 3*
Table and notes amended
Notes: 1. WP is not supported.
Description amended
BCR3 is initialized to H'0001 by a power-on reset, but is not
initialized by a manual reset or in standby mode.
Description amended of Bits 4n+3
Bits 4n+3⎯Area n (4 or 1) Read-Strobe Negate Timing
(AnRDH) (Setting Only Possible in the SH7751R): When
reading, these bits specify the timing for the negation of read
strobe. These bits should be cleared to 0 when a byte control
SRAM setting is made.
interface.
Note: n = 4 or 1
Pin
57
58
59
Bit 4n + 3: AnRDH
0
1
Corresponding
LSI Pin
—
Output from port
RDY*
2. Input an external wait request with correct polarity.
2
2
Read-Strobe Ne
Read strobe negated after hold wait cycles specified by WCR3.AnH bits
Read strobe negated according to data sampling timing
Abbrevia-
tion
BCR3
Rev.4.00 Oct. 10, 2008 Page xxi of xcviii
R/W
R/W
gate
Timing
Initial
Value
H'0001
Valid only for the SRAM
REJ09B0370-0400
(Initial value)