HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 34

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Rev.4.00 Oct. 10, 2008 Page xxxii of xcviii
REJ09B0370-0400
Item
14.5.2 Pins in DDT
Mode
Figure 14.24 shows the
system configuration in
DDT mode.
• TR:
Data Transfer Request
Format (DTR)
Figure 14.25 Data
Transfer Request
Format
Data Transfer Request
Format (DTR)
14.5.4 Notes on Use of
DDT Module
7. DTR format
14.6.3 Register
Configuration
(SH7751R)
Table 14.14 Register
Configuration
Page
555
556
557
580
581
587
Description amended
Note added
Revision (See Manual for Details)
Figure amended
A25–A0, RAS, CAS, WE, DQMn, CKE
Assertion of TR has the following different meanings.
•
Figure amended
31
Description amended, bits 31 to 29
•
Notes amended
Note: 4. When specifying data transfer requests using a
handshake protocol for channel 0, set DTR.ID = 00, DTR.MD =
00, and DTR.SZ ≠ 101, 110 for the DTR format.
Description amended
2. Normal data transfer mode (
Note: Do not use setting values other than the above.
Notes amended
Notes: *
SZ
(Reserved)
29
In normal data transfer mode (channel 0, except channel 0),
TR is asserted, and at the same time the DTR format is
output, two cycles after BAVL is asserted.
000: DTR format selected
SH7751/SH7751R
28
27
ID
26
Bit 1 of CHCR0–CHCR7 and bits 2 and 1 of
DMAOR can only be written with 0 after being read
as 1, to clear the flags.
25
MD
24
23
DBREQ/DREQ0
BAVL/DRAK0
TR/DREQ1
TDACK/DACK0
ID1, ID0/DRAK1, DACK1
CKIO
D31–D0 = DTR
Synchronous
DRAM
channel 1 to channel 3)
(Reserved)
External device
0