HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 14

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Rev.4.00 Oct. 10, 2008 Page xii of xcviii
REJ09B0370-0400
Item
3.3.7 Address Space
Identifier (ASID)
3.5.5 Avoiding
Synonym Problems
3.8 Usage Notes
4.1.1 Features
Page
77, 78
87
100
101
Description amended
Revision (See Manual for Details)
Note amended
Notes: 2. When the SH7751 is operating in single virtual
Note amended
Note: When multiple items of address translation information
Newly added
The SH7751 has an on-chip 8-Kbyte instruction cache (IC) for
instructions and 16-Kbyte operand cache (OC) for data. Half of
the memory of the operand cache (8 Kbytes) can also be used
as on-chip RAM. The features of these caches are summarized
in table 4.1.
The SH7751 has an on-chip 16-Kbyte instruction cache (IC) for
instructions and
of the operand cache memory (16 Kbytes) can also be used as
on-chip RAM. When the EMODE bit in the CCR register is
cleared to 0 in the SH7751R, both the IC and OC are set to
SH7751 compatible mode.
the CCR register is set to 1, the cache characteristics are as
shown in table 4.2...
use the same physical memory to provide for future
SuperH RISC engine family expansion, ensure that the
VPN [20:10] values are the same. Also, do not use the
same physical address for address translation
information of different page sizes.
memory mode and user mode, the LSI may hang
during hardware ITLB miss handling (see section
3.5.4, Hardware ITLB Miss Handling), or an ITLB
multiple hit exception may occur, if an ITLB miss
occurs and the UTLB contains address translation
information including an ITLB miss address with a
different ASID and unshared state (SH bit is 0). To
avoid this, use workaround (1) or (2) below.
(1) Purge the UTLB when switching the ASID
(2) Manage the behavior of program instruction
values (PTEH and ASID) of the current
processing.
addresses in user mode so that no instruction
is executed in an address area (including
overrun prefetch of an instruction) that is
registered in the UTLB with a different ASID
and unshared address translation information.
Note that accessing a different ASID in single
virtual memory mode can only be used to
trigger an exception during data access.
32-Kbyte operand cache (OC) for data. Half
When the EMODE bit in