HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 716

MPU 1.5/3.3V 0K PB-FREE 256-QFP

HD6417751RF240V

Manufacturer Part Number
HD6417751RF240V
Description
MPU 1.5/3.3V 0K PB-FREE 256-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417751RF240V

Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-QFP Exposed Pad, 256-eQFP, 256-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417751RF240V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
15. Serial Communication Interface (SCI)
Bit 6—Receive Data Register Full (RDRF): Indicates that the received data has been stored in
SCRDR1.
Bit 6: RDRF
0
1
Note: SCRDR1 and the RDRF flag are not affected and retain their previous values when an error
Bit 5—Overrun Error (ORER): Indicates that an overrun error occurred during reception,
causing abnormal termination.
Bit 5: ORER
0
1
Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in
Rev.4.00 Oct. 10, 2008 Page 616 of 1122
REJ09B0370-0400
is detected during reception or when the RE bit in SCSCR1 is cleared to 0.
If reception of the next data is completed while the RDRF flag is still set to 1, an overrun
error will occur and the receive data will be lost.
2. The receive data prior to the overrun error is retained in SCRDR1, and the data
SCSCR1 is cleared to 0.
received subsequently is lost. Serial reception cannot be continued while the ORER flag
is set to 1. In synchronous mode, serial transmission cannot be continued either.
Description
There is no valid receive data in SCRDR1
[Clearing conditions]
There is valid receive data in SCRDR1
[Setting condition]
When serial reception ends normally and receive data is transferred from
SCRSR1 to SCRDR1
Description
Reception in progress, or reception has ended normally*
[Clearing conditions]
An overrun error occurred during reception*
[Setting condition]
When the next serial reception is completed while RDRF = 1
Power-on reset, manual reset, standby mode, or module standby
When 0 is written to RDRF after reading RDRF = 1
When data in SCRDR1 is read by the DMAC
Power-on reset, manual reset, standby mode, or module standby
When 0 is written to ORER after reading ORER = 1
2
1
(Initial value)
(Initial value)

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