HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 230

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

4. Caches
1. OC data array read
2. OC data array write
4.6.5
The memory-mapped OC addresses in cache-double-mode in the SH7751R are summarized below
using data area access as an example.
• Normal mode (CCR.ORA = 0)
• RAM mode (CCR.ORA = 1)
Rev.4.00 Oct. 10, 2008 Page 130 of 1122
REJ09B0370-0400
Legend:
L:
Address field
Longword data is read into the data field from the data specified by the longword specification
bits in the address field in the OC entry corresponding to the way and entry set in the address
field.
The longword data specified in the data field is written for the data specified by the longword
specification bits in the address field in the OC entry corresponding to the way and entry set in
the address field. This write does not set the U bit to 1 on the address array side.
H'F500 0000 to H'F500 3FFF (16 KB): Way 0 (entries 0 to 511)
H'F500 4000 to H'F500 7FFF (16 KB): Way 1 (entries 0 to 511)
A shadow of the cache area occurs every 32 Kbytes up to H'F5FF FFFF.
H'F500 0000 to H'F500 1FFF (8 KB): Way 0 (entries 0 to 255)
H'F500 2000 to H'F500 3FFF (8 KB): Way 1 (entries 0 to 255)
A shadow of the cache area occurs every 16 Kbytes up to H'F5FF FFFF.
: Reserved bits (0 write value, undefined read value)
Data field
Longword specification bits
Summary of Memory-Mapped OC Addresses
:
:
31
31
1 1 1 1 0 1 0 1
Figure 4.15 Memory-Mapped OC Data Array
:
:
24
23
:
:
Longword data
15
Way
14
13
Entry
5 4
L
2 1 0
0