HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 57

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Item
D.1 Pin States
Table D.1 Pin States in
Reset, Power-Down
State, and Bus-
Released State (PCI
Enable, Disable
Common)
Table D.2 Pin States in
Reset, Power-Down
State, and Bus-
Released State (PCI
Enable)
Table D.3 Pin States in
Reset, Power-Down
State, and Bus-
Released State (PCI
Disable)
Table D.4 Handling of
Pins When PCI Is Not
Used
D.3 Note on Pin
Processing
Appendix E
Synchronous DRAM
Address Multiplexing
Tables
Appendix G Power-On
and Power-Off
Procedures
Page
1093,
1094
1095
1097
1099
1109
1115 to
1118
Revision (See Manual for Details)
Table amended
Table amended
Table amended
Table amended
Pin Name
IDSEL
Newly added
Description amended
(9) BUS 32 (64M: 4M × 4b × 4) × 8 *
(128M: 4M × 8b × 4) × 4
Replaced
PCIREQ4
PCIREQ2/MD9
PCIREQ3/MD10
WE3/IOICWR
WE2/IOICRD
Pin Name
PCIREQ4
PCIREQ2/
MD9
PCIREQ3/
MD10
Pin Name
Pin Name
DRAK1–DRAK0
MD0/SCK2
TxD
I/O
I/O
I/O
I/O
O
O
I/O
O
I/O
I/O
I
I/O
PI
I*
I*
Host
I/O
I/O
I/O
—
17
(Power On)
17
Reset
Master Slave
H
H
L
I*
PI
PZ
I*
I*
17
Non-
Host
(Power-On)
17
17
Z
I*
I*
Master Slave
Reset
17
17
Handling
Pull down to low level when IDSEL is not in use
(Power-On)
PI
PZ
PZ
L
I*
Reset
17
Host
Z*
Z*
Z*
Z
Rev.4.00 Oct. 10, 2008 Page lv of xcviii
I*
I*
10
10
10
17
17
(Manual)
Reset
Non-
Host
Z*
(IO*
Z*
(IO*
Z*
(IO*
Master Slave
O*
O*
L
I*
Z*
10
10
10
11
11
Master Slave
Z
Z
Z
4
4
11,
11,
11,
O
(Manual)
*
*
*
Reset
16
16
16
(Manual)
)
)
)
Reset
Z*
Z*
L
I*
Z*
Host
I*
I*
I*
Z
11
13
13
11
10
10
10
Z
Z
O
Standby
Non-
Host
Z*
(IO*
Z*
(IO*
Z*
(IO*
Standby
Z*
Z*
Z
I*
Z*
*
10
10
10
11
Standby
Z
Z
Z
13
13
11
11
Z*
10,
10,
10,
O*
O*
O*
O*
*
*
*
11
16
16
16
3
3
6
O*
6
)
)
)
6
PI
PI
PI
Host
Bus
Released
Z*
Z*
O
I*
O
(Software)
11
Z
Z
Z
13
13
Bus
Released
O
REJ09B0370-0400
O*
O*
Reset
PZ
(IO*
PZ
(IO*
PZ
(IO*
Non-
Host
3
3
10,
10,
10,
*
*
*
Z
Hard-
ware
Standby Notes
Z
Z
I
Z
16
16
16
Z
Z
Z
Hard-
ware
Standby Notes
)
)
)
Hard-
ware
Standby Notes
Z
Z
Z
DMAC
SCIF
SCI
Values in
paren-
thesis
are when
using
PORT
Values in
paren-
thesis
are when
using
PORT
Values in
paren-
thesis
are when
using
PORT