SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 102

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

Rev 0.2 (09-28-04)
Serial Port 1-6
Mode Register
Default = 0x00
on VCC POR,
VTR POR and
PCI RESET
■
Character timeout and RCVR FIFO trigger level interrupts have the same priority as the current
received data available interrupt; XMIT FIFO empty has the same priority as the current transmitter
holding register empty interrupt.
FIFO POLLED MODE OPERATION
With FCR bit 0 = “1” resetting IER bits 0, 1, 2 or 3 or all to zero puts the UART in the FIFO Polled
Mode of operation. Since the RCVR and XMITTER are controlled separately, either one or both can
be in the polled mode of operation. In this mode, the user’s program will check RCVR and XMITTER
status via the LSR. LSR definitions for the FIFO Polled Mode are as follows:
Bit 0=1 as long as there is one byte in the RCVR FIFO.
Bits 1 to 4 specify which error(s) have occurred. Character error status is handled the same way
as when in the interrupt mode, the IIR is not affected since EIR bit 2=0.
Bit 5 indicates when the XMIT FIFO is empty.
Bit 6 indicates that both the XMIT FIFO and shift register are empty.
Bit 7 indicates whether there are any errors in the RCVR FIFO.
There is no trigger level reached or timeout condition indicated in the FIFO Polled Mode, however, the
RCVR and XMIT FIFOs are still fully capable of holding characters.
FREQUENCY SELECTION
Each Serial Port mode register (at offset 0xF0 in Logical devices 0x4, 0x5, 0xB - 0xE) the frequency
is selected as shown in
Figure 8.2
respective logical device) on the Baud rate.
The transmitter FIFO empty indications will be delayed 1 character time minus the last stop bit time
whenever the following occurs: THRE=1 and there have not been at least two bytes at the same
time in the transmitter FIFO since the last THRE=1. The transmitter interrupt after changing FCR0
will be immediate, if it is enabled.
illustrates the effect of programming bits[3:0] of the Mode register (at offset 0xF0 in the
In all of the SP
0xF0 R/W
Devices
Logical
Table 8.3 Serial Ports Mode Register
Table
8.3.
Bit[0] MIDI Mode
= 0 MIDI support disabled (default)
= 1 MIDI support enabled
Bit[1] High Speed
= 0 High Speed Disabled (default)
= 1 High Speed Enabled
Bit [3:2] Enhanced Frequency Select
= 00 Standard Mode (default)
= 01 Select 921K
= 10 Select 1.5M
= 11 Reserved
Bit[7:4] Refer to
DATASHEET
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
86
Table 8.4
Section 8.2, "Interrupt Sharing"
summarizes this functionality.
for more detail.
SMSC SCH311X
Datasheet