SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 61

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
SMSC SCH311X
FIFO THRESHOLD EXAMPLES
1 byte
2 bytes
8 bytes
15 bytes
FIFO THRESHOLD EXAMPLES
1 byte
2 bytes
8 bytes
15 bytes
FIFO THRESHOLD EXAMPLES
1 byte
2 bytes
8 bytes
15 bytes
RESET
COND.
RESET
COND.
DIGITAL INPUT REGISTER (DIR)
Address 3F7 READ ONLY
This register is read-only in all modes.
PC-AT MODE
Bit 0 – 6 UNDEFINED
The data bus outputs D0 – 6 are read as ‘0’.
Bit 7 DSKCHG
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or
the value programmed in the Force Disk Change Register (see the Runtime Register at offset 0x1E).
PS/2 MODE
7
DSK
CHG
N/A
7
DSK
CHG
N/A
6
0
N/A
6
1
N/A
5
0
N/A
5
1
N/A
Table 7.9 FIFO Service Delay
MAXIMUM DELAY TO SERVICING AT 2 MBPS DATA RATE
1 x 4 µ s - 1.5 µ s = 2.5 µ s
2 x 4 µ s - 1.5 µ s = 6.5 µ s
8 x 4 µ s - 1.5 µ s = 30.5 µ s
15 x 4 µ s - 1.5 µ s = 58.5 µ s
MAXIMUM DELAY TO SERVICING AT 1 MBPS DATA RATE
1 x 8
2 x 8 µ s - 1.5 µ s = 14.5 µ s
8 x 8 µ s - 1.5 µ s = 62.5 µ s
15 x 8 µ s - 1.5 µ s = 118.5 µ s
MAXIMUM DELAY TO SERVICING AT 500 KBPS DATA RATE
1 x 16
2 x 16 µ s - 1.5 µ s = 30.5 µ s
8 x 16 µ s - 1.5 µ s = 126.5 µ s
15 x 16 µ s - 1.5 µ s = 238.5 µ s
DATASHEET
4
0
N/A
4
1
N/A
µs - 1.5 µs = 6.5 µs
µs - 1.5 µs = 14.5 µs
45
3
0
N/A
3
1
N/A
2
0
N/A
2
DRATE
SEL1
N/A
1
0
N/A
1
DRATE
SEL0
N/A
Rev 0.2 (09-28-04)
0
0
N/A
0
nHIGH
DENS
1