SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 93

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
Chapter 8 Serial Port (UART)
SMSC SCH311X
DLAB*
X
X
X
X
X
X
X
0
0
0
1
1
The SCH3112 incorporates two full function UARTs. The SCH3114 incorporates four full function
UARTs. The SCH3116 incorporates four full function UARTs, and two, 4 pin UARTS. They are
compatible with the NS16450, the 16450 ACE registers and the NS16C550A. The UARTS perform
serial-to-parallel conversion on received characters and parallel-to-serial conversion on transmit
characters. The data rates are independently programmable from 460.8K baud down to 50 baud. The
character options are programmable for 1 start; 1, 1.5 or 2 stop bits; even, odd, sticky or no parity;
and prioritized interrupts. The UARTs each contain a programmable baud rate generator that is capable
of dividing the input clock or crystal by a number from 1 to 65535. The UARTs are also capable of
supporting the MIDI data rate. Refer to the Configuration Registers for information on disabling, power
down and changing the base address of the UARTs. The interrupt from a UART is enabled by
programming OUT2 of that UART to a logic “1”. OUT2 being a logic “0” disables that UART’s interrupt.
The second UART also supports IrDA, HP-SIR and ASK-IR modes of operation.
Register Description
Addressing of the accessible registers of the Serial Port is shown below. The base addresses of the
serial ports are defined by the configuration registers (see
page
base addresses. The register set of the UARTS are described below.
Note: *DLAB is Bit 7 of the Line Control Register
The following section describes the operation of the registers.
RECEIVE BUFFER REGISTER (RB)
Address Offset = 0H, DLAB = 0, READ ONLY
This register holds the received incoming data byte. Bit 0 is the least significant bit, which is
transmitted and received first. Received data is double buffered; this uses an additional shift register
269). The Serial Port registers are located at sequentially increasing addresses above these
A2
0
0
0
0
0
0
1
1
1
1
0
0
A1
0
0
0
1
1
1
0
0
1
1
0
0
Table 8.1 Addressing the Serial Port
A0
0
0
1
0
0
1
0
1
0
1
0
1
DATASHEET
77
Receive Buffer (read)
Transmit Buffer (write)
Interrupt Enable (read/write)
Interrupt Identification (read)
FIFO Control (write)
Line Control (read/write)
Modem Control (read/write)
Line Status (read/write)
Modem Status (read/write)
Scratchpad (read/write)
Divisor LSB (read/write)
Divisor MSB (read/write
REGISTER NAME
Chapter 25, "Config Registers," on
Rev 0.2 (09-28-04)