SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 327

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
SMSC SCH311X
SMI_STS3
Default = 0x00
SMI_STS4
Default = 0x00
(Note
SCH3112 DEVICE
ONLY
SMI_STS4
Default = 0x00
(Note
SCH3114 DEVICE
ONLY
SMI_STS4
Default = 0x00
(Note
SCH3116 DEVICE
ONLY
SMI_EN1
Default = 0x00
on VTR POR
on VTR POR
on VTR POR
on VTR POR
On VTR POR
26.23)
26.23)
26.23)
NAME
Table 26.3 Detailed Runtime Register Description (continued)
16
(R/WC)
17
(R/WC)
17
(R/WC)
17
(R/WC)
18
(R/W)
OFFSET
(HEX)
REG
SMI Status Register 3
This register is used to read the status of the SMI inputs.
The following bits are cleared on a write of ‘1’.
Bit[0] Reserved
Bit[1] GP21
Bit[2] GP22
Bit[3] GP54
Bit[4] GP55
Bit[5] GP56
Bit[6] GP57
Bit[7] GP60
SCH3112 Device
SMI Status Register 4
This register is used to read the status of the SMI inputs.
The following bits are cleared on a write of ‘1’.
Bit[0] RESERVED
Bit[1] RESERVED
Bit[2] GP32
Bit[3] GP33
Bit[4] RESERVED
Bit[5] GP42
Bit[6] RESERVED
Bit[7] GP61
SCH3114 Device Only:
SMI Status Register 4
This register is used to read the status of the SMI inputs.
The following bits are cleared on a write of ‘1’.
Bit[0] U3INT
Bit[1] U4INT
Bit[2] GP32
Bit[3] GP33
Bit[4] RESERVED
Bit[5] GP42
Bit[6] RESERVED
Bit[7] GP61
SCH3116 Device Only:
SMI Status Register 4
This register is used to read the status of the SMI inputs.
The following bits are cleared on a write of ‘1’.
Bit[0] U3INT
Bit[1] U4INT
Bit[2] GP32
Bit[3] GP33
Bit[4] U5INT
Bit[5] GP42
Bit[6] U6INT
Bit[7] GP61
SMI Enable Register 1
This register is used to enable the different interrupt sources onto the group
nIO_SMI output.
1=Enable
0=Disable
Bit[0] EN_LOW_BAT
Bit[1] EN_PINT
Bit[2] EN_U2INT
Bit[3] EN_U1INT
Bit[4] EN_FINT
Bit[5] Reserved
Bit[6] Reserved
Bit[7] EN_WDT
DATASHEET
311
DESCRIPTION
Rev 0.2 (09-28-04)