SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 207

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
SMSC SCH311X
23.7.2
23.8
Cycle Monitoring Mode
In cycle monitoring mode, the part completes all sampling and conversions, then waits approximately
one second to repeat the process. It repeats the sampling and conversion process typically every
1.151 seconds (1.3 sec max - default averaging enabled). The sampling and conversion of each
temperature reading is performed once every monitoring cycle. This is a power saving mode.
The cycle monitoring function is started by doing a write to the Ready/Lock/Start Register, setting the
Start bit (Bit 0) high. The part then performs a “round robin” sampling of the inputs, in the order shown
above.
When the cycle monitoring function is started, it cycles through each measurement in sequence, and
it produces a converted temperature reading for each input. The state machine waits approximately
one second before repeating this process. Each measured value is compared to values stored in the
Limit registers. When the measured value violates (or is equal to) the programmed limit the Hardware
Monitor Block will set a corresponding status bit in the Interrupt Status Registers.
If auto fan option is selected, the hardware will adjust the operation of the fans accordingly.
The results of each sampling and conversion can be found in the Reading Registers and are available
at any time, however, they are only updated once per conversion cycle.
The Hardware Monitor Block contains two primary interrupt status registers (ISRs):
■
■
There is also a secondary set of interrupt status registers:
■
■
Notes:
■
■
■
These registers are used to reflect the state of all temperature and fan violation of limit error conditions
and diode fault conditions that the Hardware Monitor Block monitors.
When an error occurs during the conversion cycle, its corresponding bit is set (if enabled) in its
respective interrupt status register. The bit remains set until the register bit is written to ‘1’ by software,
at which time the bit will be cleared to ‘0’ if the associated error event no longer violates the limit
conditions or if the diode fault condition no longer exists. Writing ‘1’ to the register bit will not cause a
bit to be cleared if the source of the status bit remains active.
These registers default to 0x00 on a VCC POR, VTR POR, and Initialization. (See
SCH311X Hardware Monitor Block on page
See the description of the Interrupt Status registers in PME_STS1.
The following section defines the Interrupt Enable Bits that correspond to the Interrupt Status registers
listed above. Setting or clearing these bits affects the operation of the Interrupt Status bits.
Interrupt Status Registers
Interrupt Status Register 1 (41h)
Interrupt Status Register 2 (42h)
Interrupt Status Register 1 - Secondary (A5h)
Interrupt Status Register 2 - Secondary (A6h)
The status events in the primary set of interrupt status registers is mapped to a PME bit, an SMI
bit, to Serial IRQ (See
The nHWM_INT pin is deasserted when all of the bits in the primary ISRs (41h, 42h) are cleared.
The secondary ISRs do not affect the nHWM_INT pin.
The primary and secondary ISRs share all of the interrupt enable bits for each of the events.
Interrupt Event on Serial IRQ on page
DATASHEET
191
188.)
196), and to the nHWM_INT pin.
Rev 0.2 (09-28-04)
Resetting the