SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 252

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

Rev 0.2 (09-28-04)
24.2.11
Register
Address
41h
BIT
5-7
4
Read/
R/WC
Write
Note 24.13 This bit is set by software and cleared by hardware. Writing a ‘0’ to this register has no
Note 24.14 There is a start-up time of up to TBD ms (default - see PME_STS1) for monitoring after
1. If Start bit = '0' then:
a. Fans are set to Full On.
b. No temperature or fan tach monitoring is performed. The values in the reading registers will be N/A
c. No Status bits are set.
2. If Start bit = '1'
a. All fan control and monitoring will be based on the current values in the registers. There is no need
b. Status bits may be set.
Note: Once programmed, the register values will be saved when start bit is reset to ‘0’.
Register 41h: Interrupt Status Register 1
Note 24.15 This is a read-only bit. Writing ‘1’ to this bit has no effect.
Notes:
■
■
Reserved
NAME
VBAT
Mon
(Not Applicable), which means these values will not be considered valid readings until the Start bit
= '1'. The exception to this is the Tachometer reading registers, which always give the actual
reading on the TACH pins.
to preserve the default values after software has programmed these registers because no
monitoring or auto fan control will be done when Start bit = '0'.
This register is reset to its default value when the PWRGD_PS signal transitions high.
The is a read/write-to-clear register. Bits[6:4] are cleared on a write of one if the temperature event
is no longer active. Writing a zero to these bits has no effect.
effect.
the start bit is set to ‘1’, during which time the reading registers are not valid. Software
can poll the TRDY bit located in the Configuration Register (7Fh) to determine when the
voltage and temperature readings are valid.The following summarizes the operation of the
part based on the Start bit:
Interrupt Status 1
Register Name
R/W
R/W
R
DEFAULT
0
0
DATASHEET
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
(MSb)
24.15
Bit 7
INT2
Note
The
monitored on the next available monitoring cycle.
This is a read/write bit. Writing this bit to a ‘1’ will enable
the Vbat input to be monitored on the next available
monitoring cycle. Writing this bit to a ‘0’ has no effect. This
bit is cleared on an HVTR POR or when the Vbat register is
updated. Software can poll this bit for a ‘0’ after setting it to
a ‘1’ to determine when the Vbat register has been updated.
0 = Vbat input is not being monitored (default)
1 = Vbat input is being monitored
Note:
Reserved
236
Bit 6
Vbat Monitoring Enable
D2
The lock bit has no effect on this register bit.
Bit 5
AMB
Bit 4
D1
DESCRIPTION
Bit 3
5V
bit determines if Vbat will be
Bit 2
VCC
Bit 1
Vccp
(LSb)
SMSC SCH311X
Bit 0
2.5V
Datasheet
Default
Value
00h