SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 63

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
SMSC SCH311X
7.1.2.1
7.1.3
RESET
COND.
RESET
COND.
Configuration Control Register (CCR)
Address 3F7 WRITE ONLY
PC/AT AND PS/2 MODES
Bit 0 and 1 DATA RATE SELECT 0 and 1
These bits determine the data rate of the floppy controller. See
appropriate values.
Bit 2 – 7 RESERVED
Should be set to a logical “0”
PS/2 MODEL 30 MODE
Bit 0 and 1 DATA RATE SELECT 0 and 1
These bits determine the data rate of the floppy controller. See
appropriate values.
Bit 2 NO PRECOMPENSATION
This bit can be set by software, but it has no functionality. It can be read by bit 2 of the DSR when
in Model 30 register mode. Unaffected by software reset.
Bit 3 – 7 RESERVED
Should be set to a logical “0”
Table 7.7 on page 43
hardware reset and is unaffected by the DOR and the DSR resets.
Status Register Encoding
During the Result Phase of certain commands, the Data Register contains data bytes that give the
status of the command just executed.
7
0
N/A
7
0
N/A
6
0
N/A
6
0
N/A
shows the state of the DENSEL pin. The DENSEL pin is set high after a
5
0
N/A
5
0
N/A
DATASHEET
4
0
N/A
4
0
N/A
47
3
0
N/A
3
0
N/A
2
0
N/A
2
NOPREC
N/A
Table 7.6 on page 42
Table 7.6 on page 42
1
DRATE
SEL1
1
1
DRATE
SEL1
1
Rev 0.2 (09-28-04)
0
DRATE
SEL0
0
0
DRATE
SEL0
0
for the
for the