SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 205

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
SMSC SCH311X
23.4.3
23.5
23.6
23.7
Note: Throughout the description of the hardware monitoring block VCC POR and PWRGD_PS are
All the HWM registers will retain their value through a sleep cycle unless otherwise specified. If a VCC
POR is preceded by a VTR POR the registers will be reset to their default values (see PME_STS1).
The following is a list of the registers and bits that are reset to their default values following a VCC
POR.
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Soft Reset (Initialization)
Setting bit 7 of the Configuration Register (7Fh) performs a soft reset on all the Hardware Monitoring
registers except the reading registers. This bit is self-clearing.
The hardware monitor logic operates on a 90kHz nominal clock frequency derived from the 14MHz
clock input to the SIO block. The 14MHz clock source is also used to derive the high PWM frequencies.
The SCH311X device’s monitoring function is started by writing a ‘1’ to the START bit in the
Ready/Lock/Start Register (0x40). Measured values from the temperature sensors are stored in
Reading Registers. The values in the reading registers can be accessed via the LPC interface. These
values are compared to the programmed limits in the Limit Registers. The out-of-limit and diode fault
conditions are stored in the Interrupt Status Registers.
Note: All limit and parameter registers must be set before the START bit is set to ‘1’. Once the start
The Hardware Monitor Block supports two Monitoring modes: Continuous Mode and Cycle Mode.
These modes are selected using bit 1 of the Special Function Register (7Ch). The following
subsections contain a description of these monitoring modes.
The time to complete a conversion cycle depends upon the number of inputs in the conversion
sequence to be measured and the amount of averaging per input, which is selected using the AVG[2:0]
bits in the Special Function register (see the Special Function Register, 7Ch).
Clocks
Input Monitoring
Monitoring Modes
FANTACH1 LSB register at offset 28h
FANTACH1 MSB register at offset 29h
FANTACH2 LSB register at offset 2Ah
FANTACH2 MSB register at offset 2Bh
FANTACH3 LSB register at offset 2Ch
FANTACH3 MSB register at offset 2Dh
Bit[1] LOCK of the Ready/Lock/Start register at offset 40h
Zone 1 Low Temp Limit at offset 67h
Zone 2 Low Temp Limit at offset 68h
Zone 3 Low Temp Limit at offset 69h
Bit[3] TRDY of the Configuration register at offset 7Fh
Top Temperature Remote diode 1 (Zone 1) register at offset AEh
Top Temperature Remote diode 2 (Zone 3) register at offset AFh
Top Temperature Ambient (Zone 2) register at offset B3h
used interchangeably, since the PWRGD_PS is used to generate a VCC POR.
bit is set, these registers become read-only.
DATASHEET
189
Rev 0.2 (09-28-04)