SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 322

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

Rev 0.2 (09-28-04)
PME_EN3
Default = 0x00
PME_EN5
Default = 0x00
PME_EN6
Default = 0x00 on
VTR POR
SCH3112, SCH3114
DEVICES ONLY
NOTE: Bit 7 of this
register needs to be
VBAT powered
on VTR POR
on VTR POR
NAME
Table 26.3 Detailed Runtime Register Description (continued)
09
(R/W)
0A
(R/W)
0B
(R/W)
OFFSET
(HEX)
REG
PME Wake Status Register 3
This register is used to enable individual PME wake sources onto the
nIO_PME wake bus.
When the PME Wake Enable register bit for a wake source is active (“1”),
if the source asserts a wake event so that the associated status bit is “1”
and the PME_EN bit is “1”, the source will assert the nIO_PME signal.
When the PME Wake Enable register bit for a wake source is inactive (“0”),
the PME Wake Status register will indicate the state of the wake source but
will not assert the nIO_PME signal.
Bit[0] WDT
Bit[1] GP21
Bit[2] GP22
Bit[3] DEVINT_EN (Enable bit for group SMI signal for PME)
Bit[4] GP27
Bit[5] GP32
Bit[6] GP33
Bit[7] Reserved
The PME Wake Enable register is not affected by Vcc POR, SOFT RESET
or PCI RESET.
PME Wake Enable Register 5
This register is used to enable individual PME wake sources onto the
nIO_PME wake bus.
When the PME Wake Enable register bit for a wake source is active (“1”),
if the source asserts a wake event so that the associated status bit is “1”
and the PME_EN bit is “1”, the source will assert the nIO_PME signal.
When the PME Wake Enable register bit for a wake source is inactive (“0”),
the PME Wake Status register will indicate the state of the wake source but
will not assert the nIO_PME signal.
Bit[0] GP50
Bit[1] GP51
Bit[2] GP52
Bit[3] GP53
Bit[4] GP54
Bit[5] GP55
Bit[6] GP56
Bit[7] GP57
The PME Wake Enable register is not affected by Vcc POR, SOFT RESET
or PCI RESET.
PME Enable Register 6
This register is used to enable individual PME sources onto the nIO_PME
signal.
When the PME Enable register bit for a PME source is active (“1”), if the
source asserts a PME event and the PME_EN bit is “1”, the source will
assert the nIO_PME signal.
When the PME Enable register bit for a PME source is inactive (“0”), the
PME Status register will indicate the state of the PME source but will not
assert the nIO_PME signal.
Bit[0] LOW_BAT
Bit[1] Reserved
Bit[2] GP60
Bit[3] GP61
Bit[4] SPEMSE_EN (Wake on specific mouse click)
Bit[5] SPEKEY_EN (Wake on specific key)
Bit[6] PB_EN
Bit[7] PFR_STS Power Failure Recovery Enable
The PME Enable register 6 is not affected by VCC POR, SOFT RESET or
PCI RESET.
DATASHEET
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
306
DESCRIPTION
SMSC SCH311X
Datasheet