SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 60

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
BIT 1 RESERVED
Reserved - read returns 0
Bit 4 COMMAND BUSY
This bit is set to a 1 when a command is in progress. This bit will go active after the command byte
has been accepted and goes inactive at the end of the results phase. If there is no result phase (Seek,
Re calibrate commands), this bit is returned to a 0 after the last command byte.
Bit 5 NON-DMA
Reserved, read ‘0’. This part does not support non-DMA mode.
Bit 6 DIO
Indicates the direction of a data transfer once a RQM is set. A 1 indicates a read and a 0 indicates
a write is required.
Bit 7 RQM
Indicates that the host can transfer data if set to a 1. No access is permitted if set to a 0.
DATA REGISTER (FIFO)
Address 3F5 READ/WRITE
All command parameter information, disk data and result status are transferred between the host
processor and the floppy disk controller through the Data Register.
Data transfers are governed by the RQM and DIO bits in the Main Status Register.
The Data Register defaults to FIFO disabled mode after any form of reset. This maintains PC/AT
hardware compatibility. The default values can be changed through the Configure command (enable
full FIFO operation with threshold control). The advantage of the FIFO is that it allows the system a
larger DMA latency without causing a disk error.
Table 7.9
gives several examples of the delays with
a FIFO.
The data is based upon the following formula:
DELAY = Fifo Threshold # x DATA RATE x 8 - 1.5 µ s
At the start of a command, the FIFO action is always disabled and command parameters must be sent
based upon the RQM and DIO bit settings. As the command execution phase is entered, the FIFO is
cleared of any data to ensure that invalid data is not transferred.
An overrun or underrun will terminate the current command and the transfer of data. Disk writes will
complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to
remove the remaining data so that the result phase may be entered.
Rev 0.2 (09-28-04)
44
SMSC SCH311X
DATASHEET